Datasheet AD7683 (Analog Devices) - 6

Data Sheet AD7683 TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 5. Parameter Symbol Min Typ Max Unit
Throughput Rate tCYC 100 kHz CS Falling to DCLOCK Low tCSD 0 μs CS Falling to DCLOCK Rising tSUCS 20 ns DCLOCK Falling to Data Remains Valid tHDO 5 16 ns CS Rising Edge to DOUT High Impedance tDIS 14 100 ns DCLOCK Falling to Data Valid tEN 16 50 ns Acquisition Time tACQ 400 ns DOUT Fall Time tF 11 25 ns DOUT Rise Time tR 11 25 ns
Timing and Circuit Diagrams tCYC COMPLETE CYCLE CS tSUCS tACQ POWER DOWN DCLOCK 1 4 5 tCSD tEN t t HDO DIS HIGH-Z HIGH-Z D 0 OUT 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) NOTES
02 0
1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
1- 30
DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
04 Figure 2. Serial Interface Timing
500µA IOL TO D 1.4V OUT CL 100pF
03 0
500µA I
1-
OH
430 0 Figure 3. Load Circuit for Digital Interface Timing
2V 0.8V tEN tEN 2V 2V
-004
0.8V 0.8V
301 04 Figure 4. Voltage Reference Levels for Timing
90% DOUT 10% tR tF
04301-006 Figure 5. DOUT Rise and Fall Timing Rev. B | Page 5 of 16 Document Outline Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Terminology Typical Performance Characteristics Applications Information Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Digital Interface Layout Evaluating the AD7683 Performance Outline Dimensions Ordering Guide