Datasheet AD7684 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 100 kSPS PulSAR®, Differential ADC in MSOP |
| Páginas / Página | 17 / 6 — AD7684. TIMING SPECIFICATIONS. Table 5. Parameter Symbol. Min. Typ. Max. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 336 Kb |
| Idioma del documento | Inglés |
AD7684. TIMING SPECIFICATIONS. Table 5. Parameter Symbol. Min. Typ. Max. Unit. Timing Diagrams. tCYC. COMPLETE CYCLE. tSUCS. tACQ. POWER DOWN
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AD7684 TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 5. Parameter Symbol Min Typ Max Unit
Throughput Rate tCYC 100 kHz CS Falling to DCLOCK Low tCSD 0 μs CS Falling to DCLOCK Rising tSUCS 20 ns DCLOCK Falling to Data Remains Valid tHDO 5 16 ns CS Rising Edge to DOUT High Impedance tDIS 14 100 ns DCLOCK Falling to Data Valid tEN 16 50 ns Acquisition Time tACQ 400 ns DOUT Fall Time tF 11 25 ns DOUT Rise Time tR 11 25 ns
Timing Diagrams tCYC COMPLETE CYCLE CS tSUCS tACQ POWER DOWN DCLOCK 1 4 5 t t t t CSD EN HDO DIS Hi-Z Hi-Z D 0 OUT 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) NOTE: A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
04302-002 Figure 2. Serial Interface Timing
500
μ
A IOL TO D 1.4V OUT CL 100pF 500
μ
A IOH
04302-003 Figure 3. Load Circuit for Digital Interface Timing
2V 0.8V tDELAY tDELAY 2V 2V 0.8V 0.8V
04302-004 Figure 4. Voltage Reference Levels for Timing
90% DOUT 10% tR tF
04302-005 Figure 5. DOUT Rise and Fall Timing Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE LAYOUT EVALUATING THE PERFORMANCE OF THE AD7684 OUTLINE DIMENSIONS ORDERING GUIDE
VDD = 2.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 5. Parameter Symbol Min Typ Max Unit
Throughput Rate tCYC 100 kHz CS Falling to DCLOCK Low tCSD 0 μs CS Falling to DCLOCK Rising tSUCS 20 ns DCLOCK Falling to Data Remains Valid tHDO 5 16 ns CS Rising Edge to DOUT High Impedance tDIS 14 100 ns DCLOCK Falling to Data Valid tEN 16 50 ns Acquisition Time tACQ 400 ns DOUT Fall Time tF 11 25 ns DOUT Rise Time tR 11 25 ns
Timing Diagrams tCYC COMPLETE CYCLE CS tSUCS tACQ POWER DOWN DCLOCK 1 4 5 t t t t CSD EN HDO DIS Hi-Z Hi-Z D 0 OUT 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) NOTE: A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
04302-002 Figure 2. Serial Interface Timing
500
μ
A IOL TO D 1.4V OUT CL 100pF 500
μ
A IOH
04302-003 Figure 3. Load Circuit for Digital Interface Timing
2V 0.8V tDELAY tDELAY 2V 2V 0.8V 0.8V
04302-004 Figure 4. Voltage Reference Levels for Timing
90% DOUT 10% tR tF
04302-005 Figure 5. DOUT Rise and Fall Timing Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE LAYOUT EVALUATING THE PERFORMANCE OF THE AD7684 OUTLINE DIMENSIONS ORDERING GUIDE