Datasheet AD9216 (Analog Devices) - 10

link to page 39 AD9216 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
F T ) RE SB D_ M A _A ( DD DD X_SELEC WN HARE U 9_A 8_A 7_A 6_A 5_A 4_A 3_A AV CLK_ S M PD OEB_A DNC D D D D DRGND DRV D D D 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 PIN 1 48 D2_A INDICATOR VIN+_A 2 47 D1_A VIN–_A 3 46 D0_A (LSB) AGND 4 45 DNC AVDD 5 44 DNC REFT_A 6 43 DNC REFB_A 7 42 DNC AD9216 VREF 8 41 DRVDD TOP VIEW SENSE 9 40 DRGND (Not to Scale) REFB_B 10 39 DNC REFT_B 11 38 D9_B (MSB) AVDD 12 37 D8_B AGND 13 36 D7_B VIN–_B 14 35 D6_B VIN+_B 15 34 D5_B AGND 16 33 D4_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B ) DD _B DD DCS DFS DNC DNC DNC DNC SB 1_B 2_B 3_B L AV D D D DNC = CLK_ WN ( OEB_B DRGND DRV DO NOT CONNECT PD 0_B
04775-003
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Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 13, 16 AGND1 Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High). 20 DFS Data Output Format Select Pin. Low for offset binary; high for twos complement. 21 PDWN_B Power-Down Function Selection for Channel B. Logic 0 enables Channel B. Logic 1 powers down Channel B. (Outputs static, not High-Z.) 22 OEB_B Output Enable for Channel B. Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. 23 to 26, 39, DNC Do Not Connect Pins. Should be left floating. 42 to 45, 58 27, 30 to 38 D0_B (LSB) to Channel B Data Output Bits. D9_B (MSB) 28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF. Rev. A | Page 9 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS LOGIC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS OUTPUT CODING TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Shared Reference Mode DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE