Datasheet AD9481 (Analog Devices)

FabricanteAnalog Devices
Descripción8-Bit, 250 MSPS, 3.3 V A/D Converter
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8-Bit, 250 MSPS. 3.3 V A/D Converter. AD9481. FEATURES. FUNCTIONAL BLOCK DIAGRAM. DNL = ±0.35 LSB. VREF SENSE. AGND DRGND. DRVDD. AVDD

Datasheet AD9481 Analog Devices

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8-Bit, 250 MSPS 3.3 V A/D Converter AD9481 FEATURES FUNCTIONAL BLOCK DIAGRAM DNL = ±0.35 LSB VREF SENSE AGND DRGND DRVDD AVDD INL = ±0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) AD9481 REFERENCE Power dissipation of 439 mW at 250 MSPS PORT 8 D7A TO D0A A 1 V p-p analog input range VIN+ 8-BIT Internal 1.0 V reference T AND H 8 VIN– ADC Single-ended or differential analog inputs PIPELINE DS+ CORE PORT 8 B D7B TO D0B De-multiplexed CMOS outputs DS– Power-down mode CLK+ CLOCK DCO+ Clock duty cycle stabilizer MGMT CLK– DCO– LOGIC APPLICATIONS Digital oscilloscopes PDWN S1
05045-001
Instrumentation and measurement
Figure 1.
Communications Point-to-point radios Digital predistortion loops GENERAL DESCRIPTION
The AD9481 is available in a Pb-free, 44-lead, surface-mount package (TQFP-44) specified over the industrial temperature The AD9481 is an 8-bit, monolithic analog-to-digital converter range (−40°C to +85°C). (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a
PRODUCT HIGHLIGHTS
250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range. 1. Superior linearity. A DNL of ±0.35 makes the AD9481 suitable for many instrumentation and measurement To minimize system cost and power dissipation, the AD9481 applications includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential 2. Power-down mode. A power-down function may be exercised encode clock. No external reference or driver components are to bring total consumption down to 15 mW. required for many applications. 3. De-multiplexed CMOS outputs allow for easy interfacing The digital outputs are TTL/CMOS-compatible with an option with low cost FPGAs and standard logic. of twos complement or binary output format. The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS APPLICATIONS ANALOG INPUTS VOLTAGE REFERENCE Fixed Reference External Reference Programmable Reference CLOCKING THE AD9481 DS INPUTS DIGITAL OUTPUTS INTERLEAVING TWO AD9481s DATA CLOCK OUT POWER-DOWN INPUT AD9481 EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS GAIN OPTIONAL OPERATIONAL AMPLIFIER CLOCK OPTIONAL CLOCK BUFFER DS OPTIONAL XTAL VOLTAGE REFERENCE DATA OUTPUTS EVALUATION BOARD BILL OF MATERIALS (BOM) PCB SCHEMATICS PCB LAYERS OUTLINE DIMENSIONS ORDERING GUIDE