Datasheet AD7798, AD7799 (Analog Devices) - 9

Data Sheet AD7798/AD7799 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 16 DIN CS 2 15 DOUT/RDY AIN3(+)/P1 3 14 DVDD AD7798/ AIN3(–)/P2 4 13 AD7799 AVDD AIN1(+) 5 TOP VIEW 12 GND (Not to Scale) AIN1(–) 6 11 PSW AIN2(+) 7 10 REFIN(–) 8 9 AIN2(–) REFIN(+)
005 04856- Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous, with all data transmitted in a continuous train of pulses. Alternatively, it can be noncontinuous, with the information transmitted to or from the ADC in smaller batches of data. 2 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus, or it can be used as a frame synchronization signal when communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode, with SCLK, DIN, and DOUT/RDY used to interface with the device. 3 AIN3(+)/P1 Analog Input/Digital Output Pin. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(−). Alternatively, this pin can function as a general-purpose output bit referenced between AVDD and GND 4 AIN3(−)/P2 Analog Input/Digital Output Pin. AIN3(−) is the negative terminal of the differential analog input pair AIN3(+)/AIN3(−). Alternatively, this pin can function as a general-purpose output bit referenced between AVDD and GND 5 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 6 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 7 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(−). 8 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(−). 9 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−)) is 2.5 V, but the part can function with a reference from 0.1 V to AVDD. 10 REFIN(−) Negative Reference Input. REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere between GND and AVDD − 0.1 V. 11 PSW Low-Side Power Switch to GND. 12 GND Ground Reference Point. 13 AVDD Supply Voltage. 2.7 V to 5.25 V. 14 DVDD Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is between 2.7 V and 5.25 V. The DVDD voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V with DVDD at 3 V, or vice versa. 15 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid upon the SCLK rising edge. 16 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC, with the register selection bits of the communication register identifying the appropriate register. Rev. B | Page 9 of 28 Document Outline Features Interface Applications Functional Block Diagram General Description Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Output Noise and Resolution Specifications AD7798 AD7799 Typical Performance Characteristics On-Chip Registers Communication Register RS2, RS1, RS0 = 0, 0, 0 Status Register RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799) Mode Register RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A Configuration Register RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 Data Register RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00) ID Register RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX8 (AD7798)/0xX9 (AD7799) IO Register RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 Offset Register RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000(AD7798)/0x800000 (AD7799) Full-Scale Register RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7798)/0x5XXX00 (AD7799) ADC Circuit Information Overview Digital Interface Single-Conversion Mode Continuous-Conversion Mode Continuous Read Circuit Description Analog Input Channel Instrumentation Amplifier Bipolar/Unipolar Configuration Data Output Coding Burnout Currents Reference Reference Detect Reset AVDD Monitor Calibration Grounding and Layout Applications Information Weigh Scales Outline Dimensions Ordering Guide