Datasheet AD7933, AD7934 (Analog Devices) - 9

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AD7933/AD7934 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 DD VIN3 W/B 2 27 VIN2 DB0 3 26 VIN1 DB1 4 25 VIN0 AD7933/ DB2 5 24 VREFIN/VREFOUT AD7934 DB3 6 23 TOP VIEW AGND DB4 (Not to Scale) 7 22 CS DB5 8 21 RD DB6 9 20 WR DB7 10 19 CONVST V 11 18 DRIVE CLKIN DGND 12 17 BUSY DB8/HBEN 13 16 DB11
6 0 0
DB9 14 15 DB10
3- 71 03 Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. Decouple the supply to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. 2 W/B Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and from the AD7933/AD7934 in 10-bit words on Pin DB2 to Pin DB11, or in 12-bit words on Pin DB0 to Pin DB11. When W/B is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, tie off unused data lines to DGND. 3 to 10 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow programming of the control register. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7933, the two LSBs (DB0 and DB1) are always 0, and the LSB of the conversion result is available on DB2. 11 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7933/AD7934 operates. Decouple this pin to DGND. The voltage at this pin may be different to that at VDD but should never exceed VDD by more than 0.3 V. 12 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. Connect this pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 13 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to, or read from, the AD7933/AD7934 are on DB0 to DB3. When reading from the device, DB4 and DB5 contain the ID of the channel to which the conversion result corresponds (see the channel address bits in Table 10). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s, and the remaining six bits are conversion data. 14 to DB9 to Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the 16 DB11 control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 17 BUSY Busy Output. This is the logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY, on the 13th rising edge of CLKIN (see Figure 34). 18 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7933/AD7934 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock. 19 CONVST Conversion Start Input. A falling edge on CONVST initiates a conversion. The track-and-hold goes from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following power- down, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to power up the device. Rev. B | Page 9 of 32 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7933 SPECIFICATIONS AD7934 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CONTROL REGISTER SEQUENCER OPERATION Writing to the Control Register to Program the Sequencer CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION Traditional Multichannel Operation (SEQ0 = SEQ1 = 0) Using the Sequencer: Consecutive Sequence (SEQ0 = 1, SEQ1 = 1) REFERENCE Digital Inputs VDRIVE Input PARALLEL INTERFACE Reading Data from the AD7933/AD7934 Writing Data to the AD7933/AD7934 POWER MODES OF OPERATION Normal Mode (PM1 = PM0 = 0) Autoshutdown (PM1 = 0; PM0 = 1) Autostandby (PM1 = 1; PM0 = 0) Full Shutdown Mode (PM1 = 1; PM0 = 1) POWER vs. THROUGHPUT RATE MICROPROCESSOR INTERFACING AD7933/AD7934 to ADSP-21xx Interface AD7933/AD7934 to ADSP-21065L Interface AD7933/AD7934 to TMS32020, TMS320C25, and TMS320C5x Interface AD7933/AD7934 to 80C186 Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7933/AD7934 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE