Datasheet AD7266 (Analog Devices) - 8

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AD7266 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS E A B E V A B T T K T T K DD ND L DD IV ND L DRI OU OU DR OU OU DV V D DG D SC CS A0 DV V D DG D SC CS A0 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 DGND 1 24 A1 DGND 1 24 A1 PIN 1 REF SELECT 2 INDICATOR 23 A2 REF SELECT 2 PIN 1 23 A2 AV 3 22 DD SGL/DIFF AV 3 22 SGL/DIFF D 4 AD7266 21 RANGE DD CAPA AD7266 AGND 5 TOP VIEW 20 DCAPB D 4 CAPA 21 RANGE TOP VIEW AGND 6 (Not to Scale) 19 AGND AGND 5 (Not to Scale) 20 D V 7 18 V CAPB A1 B1 V 8 17 V AGND 6 19 AGND A2 B2 V 7 A1 18 VB1 9 10 11 12 13 14 15 16 V 8 A2 17 VB2 A3 A4 A5 A6 B6 B5 B4 B3 V V V V V V V V 9 10 11 12 13 14 15 16
1 2 -04 00
NOTES
3 3-
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP A3 A4 A5 A6 B6 B5 B4 B3
60 60
V V V V V V V V PACKAGE SHOULD BE SOLDERED TO PCB GROUND.
04 04 Figure 3. Pin Configuration (SU-32-2) Figure 2. Pin Configuration (CP-32-2)
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 29 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 2 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266 through the DCAPA and/or DCAPB pins. 3 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND. 4, 20 DCAPA, Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to DCAPB decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. The range of the external reference is dependent on the analog input range selected. 5, 6, 19 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7 to 12 VA1 to VA6 Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 6. 13 to 18 VB6 to VB1 Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 6. 21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic high when CS goes low, the analog input range is 2 × VREF. See the Analog Input Select se ion ction for details. 22 SGL/DIFF Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input Selection section for details. 23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the multiplexer for that conversion. See the Analog Input Select s ion ection for further details and Table fo 6 r multiplexer address decoding. 26 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266 and framing the serial data transfer. 27 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock is also used as the clock source for the conversion process. Rev. B | Page 7 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION OUTPUT CODING TRANSFER FUNCTIONS DIGITAL INPUTS VDRIVE MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7266 TO ADSP-218x AD7266 TO ADSP-BF53x AD7266 TO TMS320C541 AD7266 TO DSP563xx APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP EVALUATING THE AD7266 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE