Datasheet AD7266 (Analog Devices) - 6

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AD7266 TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.
Table 2. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 1 MHz min TA = −40°C to +85°C 4 MHz min TA > 85°C to 125°C 32 MHz max tCONVERT 14 × tSCLK ns max tSCLK = 1/fSCLK 437.5 ns max fSCLK = 32 MHz, VDD = 5 V, fSAMPLE = 2 MSPS 583.3 ns max fSCLK = 24 MHz, VDD = 3 V, fSAMPLE = 1.5 MSPS tQUIET 30 ns min Minimum time between end of serial read and next falling edge of CS t2 15/20 ns min VDD = 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C 20/30 ns min VDD = 5 V /3 V, CS to SCLK setup time, TA > 85°C to 125°C t3 15 ns max Delay from CS until DOUTA and DOUTB are three-state disabled t 3 4 36 ns max Data access time after SCLK falling edge, VDD = 3 V 27 ns max Data access time after SCLK falling edge, VDD = 5 V t5 0.45 tSCLK ns min SCLK low pulse width t6 0.45 tSCLK ns min SCLK high pulse width t7 10 ns min SCLK to data valid hold time, VDD = 3 V 5 ns min SCLK to data valid hold time, VDD = 5 V t8 15 ns max CS rising edge to DOUTA, DOUTB, high impedance t9 30 ns min CS rising edge to falling edge pulse width t10 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance 35 ns max SCLK falling edge to DOUTA, DOUTB, high impedance 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See Serial Interface section and Figure 41 and Figure 42. 2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. B | Page 5 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION OUTPUT CODING TRANSFER FUNCTIONS DIGITAL INPUTS VDRIVE MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7266 TO ADSP-218x AD7266 TO ADSP-BF53x AD7266 TO TMS320C541 AD7266 TO DSP563xx APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP EVALUATING THE AD7266 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE