Datasheet AD7942 (Analog Devices) - 9

FabricanteAnalog Devices
Descripción14-Bit, 250 kSPS PulSAR , Pseudo Differential ADC in MSOP/LFCSP
Páginas / Página25 / 9 — AD7942. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. REF 1. …
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AD7942. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. REF 1. 10 VIO. VDD 2. 9 SDI. IN+ 3. 8 SCK. IN– 4. 7 SDO. GND 5. 6 CNV. NOTES

AD7942 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9 SDI IN+ 3 8 SCK IN– 4 7 SDO GND 5 6 CNV NOTES

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AD7942 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9 SDI IN+ 3 AD7942 8 SCK IN– 4 7 SDO GND 5 6 CNV
4
NOTES
00
1. PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT
7- 65
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
04 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 REF AI Reference Input Voltage. The VREF range is from 0.5 V to VDD. REF is referred to the GND pin. Decouple REF as closely as possible to a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. IN+ is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF. 4 IN− AI Analog Input Ground Sense. Connect IN− to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input pin has multiple functions. On its leading edge, CNV initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, CNV enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 14 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. C | Page 8 of 24 Document Outline Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface /CS Mode 3-Wire Without Busy Indicator /CS Mode 3-Wire with Busy Indicator /CS Mode 4-Wire Without Busy Indicator /CS Mode 4-Wire with Busy Indicator Chain Mode Without Busy Indicator Chain Mode with Busy Indicator Application Hints Layout Evaluating the Performance of AD7942 Outline Dimensions Ordering Guide