Datasheet AD9229 (Analog Devices) - 8

AD9229 TIMING DIAGRAM N – 1 AIN N tA tEH tEL CLK tCPD DCO– DCO+ tFCO tFRAME FCO– FCO+ t t PD DATA D– MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9) D+
04418-002 Figure 2. Timing Diagram Rev. B | Page 7 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Power Dissipation and Power-Down Mode Digital Outputs Timing DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATE ANALOG INPUT DRIVE CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE