Datasheet AD7273, AD7274 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 3 MSPS 12-Bit A/D Converter in TSOT and MSOP Packages |
| Páginas / Página | 28 / 8 — AD7273/AD7274. TIMING EXAMPLES. Timing Example 2. Timing Example 1. … |
| Formato / tamaño de archivo | PDF / 410 Kb |
| Idioma del documento | Inglés |
AD7273/AD7274. TIMING EXAMPLES. Timing Example 2. Timing Example 1. tCONVERT. SCLK. QUIET. SDATA. ZERO. DB11. DB10. DB9. DB1. DB0. THREE-
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AD7273/AD7274 TIMING EXAMPLES Timing Example 2
For the AD7274, if CS is brought high during the 14th SCLK The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, rising edge after the two leading zeros and 12 bits of the and the throughput is 2.97 MSPS. This produces a cycle time conversion are provided, the part can achieve the fastest of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and throughput rate, 3 MSPS. If CS is brought high during the 16th tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + SCLK rising edge after the two leading zeros, 12 bits of the t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum conversion, and two trailing zeros are provided, a throughput requirement of 4 ns for tQUIET. rate of 2.97 MSPS is achievable. This is illustrated in the following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and the throughput is 3 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ. Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET, where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET, satisfying the minimum requirement of 4 ns.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t5 t8 t t 3 t 7 t 4 QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE TWO LEADING TWO TRAILING ZEROS ZEROS 1/THROUGHPUT
04973-005 Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 t5 t t t 3 7 9 t t 4 QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE TWO LEADING ZEROS 1/THROUGHPUT
04973-006 Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
t1 CS tCONVERT t2 B SCLK 1 2 3 4 5 12 13 14 15 16 t8 tQUIET 12.5(1/fSCLK) tACQUISITION 1/THROUGHPUT
04973-007 Figure 7. Serial Interface Timing 16 SCLK Cycle Rev. 0 | Page 8 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AD7274 SPECIFICATIONS AD7273 SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7273/AD7274 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7273/AD7274 TIMING EXAMPLES Timing Example 2
For the AD7274, if CS is brought high during the 14th SCLK The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, rising edge after the two leading zeros and 12 bits of the and the throughput is 2.97 MSPS. This produces a cycle time conversion are provided, the part can achieve the fastest of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and throughput rate, 3 MSPS. If CS is brought high during the 16th tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + SCLK rising edge after the two leading zeros, 12 bits of the t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum conversion, and two trailing zeros are provided, a throughput requirement of 4 ns for tQUIET. rate of 2.97 MSPS is achievable. This is illustrated in the following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and the throughput is 3 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ. Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET, where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET, satisfying the minimum requirement of 4 ns.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t5 t8 t t 3 t 7 t 4 QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE TWO LEADING TWO TRAILING ZEROS ZEROS 1/THROUGHPUT
04973-005 Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 t5 t t t 3 7 9 t t 4 QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE TWO LEADING ZEROS 1/THROUGHPUT
04973-006 Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
t1 CS tCONVERT t2 B SCLK 1 2 3 4 5 12 13 14 15 16 t8 tQUIET 12.5(1/fSCLK) tACQUISITION 1/THROUGHPUT
04973-007 Figure 7. Serial Interface Timing 16 SCLK Cycle Rev. 0 | Page 8 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AD7274 SPECIFICATIONS AD7273 SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7273/AD7274 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE