Datasheet AD9237 (Analog Devices) - 10

Data Sheet AD9237 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) Signal-To-Noise and Distortion (SINAD)1
The analog input frequency at which the spectral power of the The ratio of the rms signal amplitude to the rms value of the fundamental frequency (as determined by the FFT analysis) is sum of all other spectral components below the Nyquist reduced by 3 dB. frequency, including harmonics but excluding dc.
Aperture Delay (tA) Effective Number of Bits (ENOB)
The delay between the 50% point of the rising edge of the clock The effective number of bits for a device for sine wave inputs and the instant at which the analog input is sampled. at a given input frequency can be calculated directly from its measured SINAD using the following formula:
Aperture Jitter (tJ)
The sample-to-sample variation in aperture delay. ENOB = (SINADdBFS − 1.76)/6.02
Integral Nonlinearity (INL) Signal-to-Noise Ratio (SNR)1
The deviation of each individual code from a line drawn from The ratio of the rms signal to the rms value of the sum of all negative full scale through positive full scale. The point used other spectral components below the Nyquist frequency, as negative full scale occurs ½ LSB before the first code excluding the first six harmonics and dc. transition. Positive full scale is defined as a level 1½ LSBs
Spurious-Free Dynamic Range (SFDR)1
beyond the last code transition. The deviation is measured SFDR is the difference in dB between the rms amplitude of the from the middle of each particular code to the true straight line. input signal and the rms value of the peak spurious signal. The
Differential Nonlinearity (DNL, No Missing Codes)
peak spurious signal may not be an harmonic. An ideal ADC exhibits code transitions that are exactly 1 LSB
Two-Tone SFDR1
apart. DNL is the deviation from this ideal value. Guaranteed The ratio of the rms value of either input tone to the rms value no missing codes to 12-bit resolution indicates that al 4096 of the peak spurious component. The peak spurious component codes must be present over al operating ranges. may or may not be an IMD product.
Offset Error Clock Pulse Width and Duty Cycle
The major carry transition should occur for an analog value Pulse width high is the minimum amount of time that the clock ½ LSB below VIN+ = VIN–. Offset error is defined as the pulse should be left in the Logic 1 state to achieve rated deviation of the actual transition from that point. performance. Pulse width low is the minimum time the clock
Gain Error
pulse should be left in the low state. At a given clock rate, these The first code transition should occur at an analog value specifications define an acceptable clock duty cycle. ½ LSB above negative full scale. The last transition should occur
Minimum Conversion Rate
at an analog value 1½ LSB below the positive full scale. Gain The clock rate at which the SNR of the lowest analog signal error is the deviation of the actual difference between first and frequency drops by no more than 3 dB below the guaranteed last code transitions and the ideal difference between first and limit. last code transitions.
Maximum Conversion Rate Temperature Drift
The clock rate at which parametric testing is performed. The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value
Output Propagation Delay (tPD)
at TMIN or TMAX. The delay between the clock logic threshold and the time when all bits are within valid logic levels.
Power Supply Rejection Ratio
The change in ful scale from the value with the supply at the
Out-of-Range Recovery Time
minimum limit to the value with the supply at its maximum The time it takes the ADC to reacquire the analog input after a limit. transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10%
Total Harmonic Distortion (THD)
1 below positive full scale. The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. C | Page 9 of 24 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications DC Specifications Digital Specifications AC Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Equivalent Circuits Typical Performance Characteristics Applying the AD9237 Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Power Dissipation, Power Scaling, and Standby Mode Digital Outputs Operational Mode Selection Out of Range (OTR) Digital Output Enable Function (OE) Timing Outline Dimensions Ordering Guide