Datasheet AD9445 (Analog Devices)

14-Bit, 105/125 MSPS, IF Sampling ADC AD9445 FEATURES FUNCTIONAL BLOCK DIAGRAM 125 MSPS guaranteed sampling rate (AD9445BSV-125) AGND AVDD1 AVDD2 DRGND DRVDD 78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p) RF ENABLE AD9445 74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p) DFS DCS MODE 77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p) BUFFER VIN+ 14 OUTPUT MODE PIPELINE 2 74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p) T/H CMOS OR VIN– ADC OR 73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p) LVDS 28 OUTPUT D13 TO D0 102 dBFS 2-tone SFDR with 30 MHz and 31 MHz STAGING 2 92 dBFS 2-tone SFDR with 170 MHz and 171 MHz CLOCK CLK+ DCO AND TIMING REF 60 fsec rms jitter CLK– MANAGEMENT Excellent linearity DNL = ±0.25 LSB typical VREF SENSE REFT REFB
05489-001
INL = ±0.8 LSB typical
Figure 1.
2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement)
Optional features allow users to implement various selectable
Output clock available
operating conditions, including input range, data format select,
3.3 V and 5 V supply operation
high IF sampling mode, and output data mode. The AD9445 is available in a Pb-free, 100-lead, surface-mount,
APPLICATIONS
plastic package (100-lead TQFP/EP) specified over the
Multicarrier, multimode cellular receivers
industrial temperature range −40°C to +85°C.
Antenna array positioning Power amplifier linearization PRODUCT HIGHLIGHTS Broadband wireless Radar
1. High performance: outstanding SFDR performance for IF
Infrared imaging
sampling applications such as multicarrier, multimode 3G,
Medical imaging
and 4G cellular base station receivers.
Communications instrumentation
2. Ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an
GENERAL DESCRIPTION
output clock simplifies data capture. The AD9445 is a 14-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip IF sampling track-and-hold 3. Packaged in a Pb-free, 100-lead TQFP/EP package. circuit. It is optimized for performance, small size, and ease of 4. Clock duty cycle stabilizer (DCS) maintains overall ADC use. The product operates at up to a 125 MSPS conversion rate performance over a wide range of clock pulse widths. and is designed for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. 5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. 6. RF enable pin allows users to configure the device for No external reference or driver components are required for optimum SFDR when sampling frequencies above 210 MHz many applications. Data outputs are CMOS or LVDS (AD9445-125) or 240 MHz (AD9445-105). compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TERMINOLOGY PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs High IF Applications CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer RF ENABLE EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE