Datasheet AD9233 (Analog Devices) - 6

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AD9233 AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.
Table 2. AD9233BCPZ-80 AD9233BCPZ-105 AD9233BCPZ-125 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz 25°C 69.5 69.5 69.5 dBc fIN = 70 MHz 25°C 69.5 69.5 69.5 dBc Full 68.9 68.3 68.3 dBc fIN = 100 MHz 25°C 69.4 69.4 69.4 dBc fIN = 170 MHz 25°C 68.9 68.9 68.9 dBc SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz 25°C 69.2 69.2 69.2 dBc fIN = 70 MHz 25°C 69.2 69.2 69.2 dBc Full 68.5 67.3 67.3 dBc fIN = 100 MHz 25°C 69.1 69.1 69.1 dBc fIN = 170 MHz 25°C 68.6 68.6 68.6 dBc EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 11.4 11.4 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 11.4 Bits fIN = 100 MHz 25°C 11.4 11.4 11.4 Bits fIN = 170 MHz 25°C 11.3 11.3 11.3 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz 25°C −90.0 −90.0 −90.0 dBc fIN = 70 MHz 25°C −85.0 −85.0 −85.0 dBc Full −76.0 −73.0 −73.0 dBc fIN = 100 MHz 25°C −85.0 −85.0 −85.0 dBc fIN = 170 MHz 25°C −83.5 −83.5 −83.5 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz 25°C 90.0 90.0 90.0 dBc fIN = 70 MHz 25°C 85.0 85.0 85.0 dBc Full 76.0 73.0 73.0 dBc fIN = 100 MHz 25°C 85.0 85.0 85.0 dBc fIN = 170 MHz 25°C 83.5 83.5 83.5 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 2.4 MHz 25°C −90.0 −90.0 −90.0 dBc fIN = 70 MHz 25°C −90.0 −90.0 −90.0 dBc Full −85.0 −81.0 −81.0 dBc fIN = 100 MHz 25°C −90.0 −90.0 −90.0 dBc fIN = 170 MHz 25°C −90.0 −90.0 −90.0 dBc TWO-TONE SFDR fIN = 30 MHz (−7 dBFS), 31 MHz (−7 dBFS) 25°C 87 87 85 dBFS fIN = 170 MHz (−7 dBFS), 171 MHz (−7 dBFS) 25°C 83 83 84 dBFS ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz 1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. A | Page 5 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Clock Duty Cycle JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE Power-Down Mode Standby Mode DIGITAL OUTPUTS Out-of-Range (OR) Condition Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels SPI-Accessible Features LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN VREF RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS (BOM) OUTLINE DIMENSIONS ORDERING GUIDE