Datasheet AD9461 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 130 MSPS A/D Converter |
| Páginas / Página | 29 / 5 — AD9461. AC SPECIFICATIONS. Table 2. AD9461BSVZ. Parameter. Temp. Min Typ … |
| Formato / tamaño de archivo | PDF / 714 Kb |
| Idioma del documento | Inglés |
AD9461. AC SPECIFICATIONS. Table 2. AD9461BSVZ. Parameter. Temp. Min Typ Max Unit
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 21
AD9461 AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 2. AD9461BSVZ Parameter Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz 25°C 76.3 77.7 dB Full 76.0 dB fIN = 170 MHz1 25°C 74.2 76.0 dB Full 73.8 dB fIN = 225 MHz 25°C 74.4 dB fIN = 225 MHz @125 MSPS 25°C 75.3 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25°C 74.0 76.7 dB Full 74.0 dB fIN = 170 MHz1 25°C 71.9 75.1 dB Full 68.3 dB fIN = 225 MHz 25°C 73.5 dB fIN = 225 MHz @125 MSPS 25°C 74.6 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 12.5 Bits fIN = 170 MHz1 25°C 12.2 Bits fIN = 225 MHz 25°C 11.9 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC) fIN = 10 MHz 25°C 82 90 dBc Full 80 dBc fIN = 170 MHz1 25°C 77 84 dBc Full 71 dBc fIN = 225 MHz 25°C 82 dBc fIN = 225 MHz @125 MSPS 25°C 86 dBc WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fIN = 10 MHz 25°C 88 96 dBc Full 86 dBc fIN = 170 MHz1 25°C 89 95 dBc Full 85 dBc fIN = 225 MHz 25°C 91 dBc fIN = 225 MHz @ 125 MSPS 25°C 93 dBc TWO-TONE SFDR fIN = 169.6 MHz @ −7 dBFS, 170.6 MHz @ −7 dBFS 25°C 89 dBFS ANALOG BANDWIDTH Full 615 MHz 1 SFDR = high (AVDD1). See the Operational Mode Selection section. Rev. 0 | Page 4 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9461 AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS on, SFDR = AGND, unless otherwise noted.
Table 2. AD9461BSVZ Parameter Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz 25°C 76.3 77.7 dB Full 76.0 dB fIN = 170 MHz1 25°C 74.2 76.0 dB Full 73.8 dB fIN = 225 MHz 25°C 74.4 dB fIN = 225 MHz @125 MSPS 25°C 75.3 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25°C 74.0 76.7 dB Full 74.0 dB fIN = 170 MHz1 25°C 71.9 75.1 dB Full 68.3 dB fIN = 225 MHz 25°C 73.5 dB fIN = 225 MHz @125 MSPS 25°C 74.6 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 12.5 Bits fIN = 170 MHz1 25°C 12.2 Bits fIN = 225 MHz 25°C 11.9 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC) fIN = 10 MHz 25°C 82 90 dBc Full 80 dBc fIN = 170 MHz1 25°C 77 84 dBc Full 71 dBc fIN = 225 MHz 25°C 82 dBc fIN = 225 MHz @125 MSPS 25°C 86 dBc WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fIN = 10 MHz 25°C 88 96 dBc Full 86 dBc fIN = 170 MHz1 25°C 89 95 dBc Full 85 dBc fIN = 225 MHz 25°C 91 dBc fIN = 225 MHz @ 125 MSPS 25°C 93 dBc TWO-TONE SFDR fIN = 169.6 MHz @ −7 dBFS, 170.6 MHz @ −7 dBFS 25°C 89 dBFS ANALOG BANDWIDTH Full 615 MHz 1 SFDR = high (AVDD1). See the Operational Mode Selection section. Rev. 0 | Page 4 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE