Datasheet AD7796, AD7797 (Analog Devices) - 5

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Data Sheet AD7796/AD7797 TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2. Parameter1, 2 Limit at TMIN, TMAX (B Version) Unit Test Conditions/Comments
t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width Read Operation t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 3 2 0 ns min SCLK active edge to data valid delay4 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 5, 6 5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t6 0 ns min SCLK inactive edge to CS inactive edge t7 10 ns min SCLK inactive edge to DOUT/RDY high Write Operation t8 0 ns min CS falling edge to SCLK active edge setup time4 t9 30 ns min Data valid to SCLK edge setup time t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the devices and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. Care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT 1.6V PIN 50pF I
002
SOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V)
06083- Figure 2. Load Circuit for Timing Characterization Rev. B | Page 5 of 24 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RMS NOISE AND RESOLUTION SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATION REGISTER RS2, RS1, RS0 = 0, 0, 0 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 DATA REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000 (AD7796)/0x000000 (AD7797) ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0x5A (AD7796)/0x5B (AD7797) OFFSET REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7796)/0x800000 (AD7797) FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7796)/0x5XXX00 (AD7797) ADC CIRCUIT INFORMATION OVERVIEW DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE RESET BURNOUT CURRENTS AVDD MONITOR TEMPERATURE MONITOR CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE