Datasheet AD9259 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC |
| Páginas / Página | 53 / 6 — Data Sheet. AD9259. AC SPECIFICATIONS. Table 2. Parameter. Temperature. … |
| Revisión | E |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
Data Sheet. AD9259. AC SPECIFICATIONS. Table 2. Parameter. Temperature. Min. Typ. Max. Unit
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 8 link to page 6
Data Sheet AD9259 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2. Parameter 1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 73.5 dB fIN = 19.7 MHz Full 71.0 73.0 dB fIN = 70 MHz Full 72.8 dB SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 72.7 dB fIN = 19.7 MHz Full 70.2 72.2 dB fIN = 70 MHz Full 72.0 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 11.92 Bits fIN = 19.7 MHz Full 11.5 11.85 Bits fIN = 70 MHz Full 11.8 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 84 dBc fIN = 19.7 MHz Full 73 84 dBc fIN = 70 MHz Full 78 dBc WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −88 dBc fIN = 19.7 MHz Full −84 −73 dBc fIN = 70 MHz Full −78 dBc WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 dBc fIN = 19.7 MHz Full −90 −80 dBc fIN = 70 MHz Full −88 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 dBc fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 80.0 dBc 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. Rev. E | Page 5 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
Data Sheet AD9259 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2. Parameter 1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 73.5 dB fIN = 19.7 MHz Full 71.0 73.0 dB fIN = 70 MHz Full 72.8 dB SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 72.7 dB fIN = 19.7 MHz Full 70.2 72.2 dB fIN = 70 MHz Full 72.0 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 11.92 Bits fIN = 19.7 MHz Full 11.5 11.85 Bits fIN = 70 MHz Full 11.8 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 84 dBc fIN = 19.7 MHz Full 73 84 dBc fIN = 70 MHz Full 78 dBc WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −88 dBc fIN = 19.7 MHz Full −84 −73 dBc fIN = 70 MHz Full −78 dBc WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 dBc fIN = 19.7 MHz Full −90 −80 dBc fIN = 70 MHz Full −88 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 dBc fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 80.0 dBc 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. Rev. E | Page 5 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide