Datasheet AD9460 (Analog Devices)

16-Bit, 80 MSPS/105 MSPS ADC AD9460 FEATURES FUNCTIONAL BLOCK DIAGRAM 105 MSPS guaranteed sampling rate (AD9460-105) AGND AVDD1 AVDD2 DRGND DRVDD 79.4 dBFS SNR/91 dBc SFDR with 10 MHz input AD9460 DFS (3.4 V p-p input, 80 MSPS) DCS MODE 78.3 dBFS SNR/ with 170 MHz input BUFFER OUTPUT MODE VIN+ 16 (4.0 V p-p input, 80 MSPS) 2 T/H PIPELINE CMOS OR VIN– ADC OR 77.8 dBFS SNR/87 dBc SFDR with 170 MHz input LVDS 32 OUTPUT D15 TO D0 (3.4 V p-p input, 80 MSPS) STAGING 77.2 dBFS SNR/84 dBc SFDR with 170 MHz input 2 CLK+ CLOCK DCO (3.4 V p-p input, 105 MSPS) AND TIMING CLK– MANAGEMENT REF 90 dBFS two-tone SFDR with 139 MHz/140 MHz input (3.4 V p-p input, 105 MSPS)
001 6-
60 fsec rms jitter VREF SENSE REFT REFB
0600
Excellent linearity
Figure 1.
DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available 3.3 V and 5 V supply operation
Optional features allow users to implement various selectable
APPLICATIONS
operating conditions, including input range, data format select,
MRI receivers
and output data mode.
Multicarrier, multimode, cellular receivers
The AD9460 is available in a Pb-free, 100-lead, surface-mount,
Antenna array positioning
plastic package (TQFP_EP) specified over the industrial tem-
Power amplifier linearization
perature range of −40°C to +85°C.
Broadband wireless Radar Infrared imaging PRODUCT HIGHLIGHTS Communications instrumentation
1. True 16-bit linearity.
GENERAL DESCRIPTION
2. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital magnetic resonance imaging, and radar receivers. converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The 3. Ease of use: on-chip reference and high input impedance, AD9460 operates up to 105 MSPS, providing a superior signal- track-and-hold with adjustable analog input range, and an to-noise ratio (SNR) for instrumentation, medical imaging, and output clock simplifies data capture. radar receivers using baseband (<100 MHz) and IF frequencies. 4. Packaged in a Pb-free, 100-lead TQFP/EP. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC No external reference or driver components are required for performance over a wide range of clock pulse widths. many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the 6. Out-of-range (OR) outputs indicate when the signal is overall current needed for short trace distances. beyond the selected input range.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW Internal Reference Connection Internal Reference Trim External Reference Operation Analog Inputs CLOCK INPUT CONSIDERATIONS Jitter Considerations POWER CONSIDERATIONS DIGITAL OUTPUTS LVDS Mode CMOS Mode TIMING OPERATIONAL MODE SELECTION Data Format Select Output Mode Select Duty Cycle Stabilizer SFDR Enhancement EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE