Datasheet AD9254 (Analog Devices) - 5

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AD9254 AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted.
Table 2. AD9254BCPZ-150 Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz 25°C 72.0 dBc fIN = 70 MHz 25°C 71.8 dBc Full 70.0 dBc fIN = 100 MHz 25°C 71.6 dBc fIN = 170 MHz 25°C 70.8 dBc SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz 25°C 71.7 dBc fIN = 70 MHz 25°C 71.0 dBc Full 69.0 dBc fIN = 100 MHz 25°C 70.6 dBc fIN = 170 MHz 25°C 69.8 dBc EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz 25°C 11.7 Bits fIN = 70 MHz 25°C 11.7 Bits fIN = 100 MHz 25°C 11.6 Bits fIN = 170 MHz 25°C 11.5 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz 25°C −90 dBc fIN = 70 MHz 25°C −84 dBc Full −74 dBc fIN = 100 MHz 25°C −83 dBc fIN = 170 MHz 25°C −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz 25°C 90 dBc fIN = 70 MHz 25°C 84 dBc Full 74 dBc fIN = 100 MHz 25°C 83 dBc fIN = 170 MHz 25°C 80 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 2.4 MHz 25°C −93 dBc fIN = 70 MHz 25°C −93 dBc Full −85 dBc fIN = 100 MHz 25°C −90 dBc fIN = 170 MHz 25°C −90 dBc TWO-TONE SFDR fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 90 dBFS fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 90 dBFS ANALOG INPUT BANDWIDTH 25°C 650 MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. 0 | Page 4 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS JITTER CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING SERIAL PORT INTERFACE (SPI) MEMORY MAP READING THE MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER TABLE LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS CML RBIAS REFERENCE DECOUPLING EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE