link to page 33 link to page 9 link to page 18 link to page 9 link to page 18 link to page 12 link to page 12 link to page 12 link to page 12 AD7634Data SheetPIN CONFIGURATION AND FUNCTION DESCRIPTIONSINDFNBUFPDGFMDNDCFFDBUFDRE+–PPRETEAVINAGVEEVCINRERE48 47 46 45 44 43 42 41 40 39 38 37AGND 136BIPOLARAVDDPIN 1235 CNVSTMODE0 334 PDMODE1 433 RESETD0/OB/2C 532 CSAD7634WARP 631 RDTOP VIEWIMPULSE 730(Not to Scale)TEND1/A0 829 BUSYD2/A1 928 D17/SCCSD3 1027 D16/SCCLKD4/DIVSCLK[0] 1126 D15/SCIND5/DIVSCLK[1] 1225 D14/HW/SW13 14 15 16 17 18 19 20 21 22 23 24KNDDT UKCR/INTNCLDINDDDNDOTYCSOXSSOGOVDVDGDDCLRRESS12/SYN/INVINV0/D6/11/DRDED7D8/9/RDC/D1D -004 D3/ 406 D1 06 NOTES 1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No.MnemonicType1 Description 1, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be refer- enced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 3, 4 MODE[0:1] DI Data Input/Output Interface Mode Selection. Interface ModeMODE1MODE0Description 0 Low Low 18-bit interface 1 Low High 16-bit interface 2 High Low 8-bit (byte) interface 3 High High Serial interface 5 D0/OB/2C DI/O2 In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos complement. When OB/2C = high, the digital output is straight binary When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI2 Conversion Mode Selection. See the Modes of Operation section for a more detailed description. Used in conjunction with the IMPULSE input per the following: Conversion ModeWARPIMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High 7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation section for a more detailed description. Rev. B | Page 8 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Warp Mode Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure Single-to-Differential Driver VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V)(PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 18-Bit Interface (Master or Slave) 16-Bit and 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (MODE[1:0] = 3, EXT/ = Low) Read During Convert (RDC = High) Read After Covert (RDC = Low, DIVSCLK[1:0] = 0 to 3) SLAVE SERIAL INTERFACE External Clock (MODE[1:0] = 3, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE