Datasheet AD7366, AD7367 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | True Bipolar Input, Dual 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC |
| Páginas / Página | 28 / 7 — AD7366/AD7367. TIMING SPECIFICATIONS. Table 4. Limit at T. , T. MIN. MAX. … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 464 Kb |
| Idioma del documento | Inglés |
AD7366/AD7367. TIMING SPECIFICATIONS. Table 4. Limit at T. , T. MIN. MAX. Parameter 2.7 V ≤ V. < 4.75 V. 4.75 V ≤ V. ≤ 5.25 V. DRIVE. Unit
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AD7366/AD7367 TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = −16.5 V to −11.5 V, VDRIVE = 2.7 V to 5.25 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4. Limit at T , T MIN MAX Parameter 2.7 V ≤ V < 4.75 V 4.75 V ≤ V ≤ 5.25 V DRIVE DRIVE Unit Test Conditions/Comments
t Conversion time, internal clock; CONVERT CNVST falling edge to BUSY falling edge 680 680 ns max AD7367 610 610 ns max AD7366 f 10 10 kHz min Frequency of serial read clock SCLK 35 48 MHz max t 30 30 ns min Minimum quiet time required between the end of serial QUIET read and the start of the next conversion t 10 10 ns min Minimum 1 CNVST low pulse t 40 40 ns min 2 CNVST falling edge to BUSY rising edge t 0 0 ns min BUSY falling edge to MSB, valid when prior 3 CS is low for t4 to BUSY going low t 10 10 ns max Delay from A) and Pin 23 4 CS falling edge until Pin 1 (DOUT (D B) are three-state disabled OUT t 2 20 14 ns max Data access time after SCLK falling edge 5 t 7 7 ns min SCLK to data valid hold time 6 t 0.3 × t 0.3 × t ns min SCLK low pulse width 7 SCLK SCLK t 0.3 × t 0.3 × t ns min SCLK high pulse width 8 SCLK SCLK t 10 10 ns max A, D B, high impedance 9 CS rising edge to DOUT OUT t 70 70 µs max Power-up time from shutdown mode; time required POWER-UP between CNVST rising edge and CNVST falling edge 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology section, Figure 25, and Figure 26. 2 The time required for the output to cross is 0.4 V or 2.4 V. Rev. D | Page 7 of 28 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Analog Inputs Transfer Function Track-and-Hold Typical Connection Diagram Driver Amplifier Choice VDRIVE Reference Modes of Operation Normal Mode Shutdown Mode Power-Up Times Serial Interface Microprocessor Interfacing AD7366/AD7367 to ADSP-218x AD7366/AD7367 to ADSP-BF53x AD7366/AD7367 to TMS320VC5506 AD7366/AD7367 to DSP563xx Application Hints Layout and Grounding Outline Dimensions Ordering Guide
AD7366/AD7367 TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = −16.5 V to −11.5 V, VDRIVE = 2.7 V to 5.25 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4. Limit at T , T MIN MAX Parameter 2.7 V ≤ V < 4.75 V 4.75 V ≤ V ≤ 5.25 V DRIVE DRIVE Unit Test Conditions/Comments
t Conversion time, internal clock; CONVERT CNVST falling edge to BUSY falling edge 680 680 ns max AD7367 610 610 ns max AD7366 f 10 10 kHz min Frequency of serial read clock SCLK 35 48 MHz max t 30 30 ns min Minimum quiet time required between the end of serial QUIET read and the start of the next conversion t 10 10 ns min Minimum 1 CNVST low pulse t 40 40 ns min 2 CNVST falling edge to BUSY rising edge t 0 0 ns min BUSY falling edge to MSB, valid when prior 3 CS is low for t4 to BUSY going low t 10 10 ns max Delay from A) and Pin 23 4 CS falling edge until Pin 1 (DOUT (D B) are three-state disabled OUT t 2 20 14 ns max Data access time after SCLK falling edge 5 t 7 7 ns min SCLK to data valid hold time 6 t 0.3 × t 0.3 × t ns min SCLK low pulse width 7 SCLK SCLK t 0.3 × t 0.3 × t ns min SCLK high pulse width 8 SCLK SCLK t 10 10 ns max A, D B, high impedance 9 CS rising edge to DOUT OUT t 70 70 µs max Power-up time from shutdown mode; time required POWER-UP between CNVST rising edge and CNVST falling edge 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology section, Figure 25, and Figure 26. 2 The time required for the output to cross is 0.4 V or 2.4 V. Rev. D | Page 7 of 28 Document Outline Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Analog Inputs Transfer Function Track-and-Hold Typical Connection Diagram Driver Amplifier Choice VDRIVE Reference Modes of Operation Normal Mode Shutdown Mode Power-Up Times Serial Interface Microprocessor Interfacing AD7366/AD7367 to ADSP-218x AD7366/AD7367 to ADSP-BF53x AD7366/AD7367 to TMS320VC5506 AD7366/AD7367 to DSP563xx Application Hints Layout and Grounding Outline Dimensions Ordering Guide