Datasheet AD7366-5, AD7367-5 (Analog Devices) - 9

link to page 22 link to page 17 link to page 17 link to page 16 link to page 16
AD7366-5/AD7367-5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DOUTA 1 24 DGND V 2 23 DRIVE DOUTB DV 3 CC 22 BUSY RANGE1 4 AD7366-5/ 21 CNVST RANGE0 AD7367-5 5 20 SCLK ADDR TOP VIEW 6 19 CS (Not to Scale) AGND 7 18 REFSEL AV 8 17 AGND CC DCAPA 9 16 DCAPB VSS 10 15 VDD V 11 14 A1 V
2
B1
00
V 12 13
2-
A2 VB2
84 06 Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 23 DOUTA, DOUTB Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366-5 while 14 SCLK cycle are required for the AD7367-5. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366-5 and 14 bits for the AD7367-5 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles for the AD7367-5, on either DOUTA or DOUTB, the data from the other ADC follows on that DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. See the Serial Interf sec ace tion for more information. 2 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different than the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V. 3 DVCC Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V, even on a transient basis. This supply should be decoupled to DGND. Place 10 μF and 100 nF decoupling capacitors on the DVCC pin. 4, 5 RANGE1, Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog RANGE0 input channels. See the Analog Inputs section and Table 8 for details. 6 ADDR Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion. 7, 17 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7366-5/AD7367-5. All analog input signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 8 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to AGND. Place 10 μF and 100 nF decoupling capacitors on the AVCC pin. 9, 16 DCAPA, DCAPB Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 10 VSS Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure of the AD7366-5/AD7367-5. The supply must be less than or equal to −5 V (see Table 7 for further details). Place 10 μF and 100 nF decoupling capacitors on the VSS pin. 11, 12 VA1, VA2 Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels is determined by the RANGE0 and RANGE1 pins. 13, 14 VB2, VB1 Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels is determined by the RANGE0 and RANGE1 pins. 15 VDD Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure of the AD7366-5/AD7367-5. The supply must be greater than or equal to 5 V (see Table 7 for further details). Place 10 μF and 100 nF decoupling capacitors on the VDD pin. Rev. B | Page 9 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7366-5 SPECIFICATIONS AD7367-5 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUTS TRANSFER FUNCTION Track-and-Hold TYPICAL CONNECTION DIAGRAM DRIVER AMPLIFIER CHOICE VDRIVE REFERENCE MODES OF OPERATION NORMAL MODE SHUTDOWN MODE POWER-UP TIMES SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7366-5/AD7367-5 TO ADSP-218x AD7366-5/AD7367-5 TO ADSP-BF53x AD7366-5/AD7367-5 TO TMS320VC5506 AD7366-5/AD7367-5 TO DSP563xx APPLICATION HINTS LAYOUT AND GROUNDING EVALUATING THE AD7366-5/AD7367-5 OUTLINE DIMENSIONS ORDERING GUIDE