Datasheet AD7766 (Analog Devices) - 6

link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6
AD7766 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF+ = 5 V, common-mode input = VREF+/2, TA = −40°C (TMIN) to +105°C (TMAX), unless otherwise noted.1
Table 3. Parameter Limit at tMIN, tMAX Unit Description
DRDY OPERATION t1 510 ns typ MCLK rising edge to DRDY falling edge t 2 2 100 ns min MCLK high pulse width t 2 3 900 ns max MCLK low pulse width t4 265 ns typ MCLK rising edge to DRDY rising edge (AD7766) 128 ns typ MCLK rising edge to DRDY rising edge (AD7766-1) 71 ns typ MCLK rising edge to DRDY rising edge (AD7766-2) t5 294 ns typ DRDY pulse width (AD7766) 435 ns typ DRDY pulse width (AD7766-1) 492 ns typ DRDY pulse width (AD7766-2) t 3 READ t − t DRDY 5 ns typ DRDY low period, read data during this period t 3 n × 8 × t DRDY MCLK ns typ DRDY period READ OPERATION t6 0 ns min DRDY falling edge to CS setup time t7 6 ns max CS falling edge to SDO tristate disabled t8 60 ns max Data access time after SCLK falling edge (VDRIVE = 1.7 V) 50 ns max Data access time after SCLK falling edge (VDRIVE = 2.3 V) 25 ns max Data access time after SCLK falling edge (VDRIVE = 2.7 V) 24 ns max Data access time after SCLK falling edge (VDRIVE = 3.0 V) t9 10 ns min SCLK falling edge to data valid hold time (VDRIVE = 3.6 V) t10 10 ns min SCLK high pulse width t11 10 ns min SCLK low pulse width tSCLK 1/t8 sec min Minimum SCLK period t12 6 ns max Bus relinquish time after CS rising edge t13 0 ns min CS rising edge to DRDY rising edge READ OPERATION WITH CS LOW t14 0 ns min DRDY falling edge to data valid setup time t15 0 ns max DRDY rising edge to data valid hold time DAISY-CHAIN OPERATION t16 1 ns min SDI valid to SCLK falling edge setup time t17 2 ns max SCLK falling edge to SDI valid hold time SYNC/PD OPERATION t18 1 ns typ SYNC/PD falling edge to MCLK rising edge t19 20 ns typ MCLK rising edge to DRDY rising edge going into SYNC/PD mode t20 1 ns min SYNC/PD rising edge to MCLK rising edge t21 510 ns typ MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode t 3 SETTLING (592 × n) + 2 tMCLK Filter settling time after a reset or power-down 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V. 2 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum MCLK frequency is 1.024 MHz. 3 n = 1 for AD7766, n = 2 for the AD7766-1, n = 4 for the AD7766-2. Rev. C | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION AD7766/AD7766-1/AD7766-2 TRANSFER FUNCTION CONVERTER OPERATION ANALOG INPUT STRUCTURE SUPPLY AND REFERENCE VOLTAGES AD7766/AD7766-1/AD77662-2 INTERFACE INITIAL POWER-UP READING DATA POWER-DOWN, RESET, AND SYNCHRONIZATION DAISY CHAINING READING DATA IN DAISY-CHAIN MODE CHOOSING THE SCLK FREQUENCY DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS DRIVING THE AD7766/AD7766-1/AD7766-2 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SIGNAL SOURCE ANTIALIASING POWER DISSIPATION VREF+ INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS OUTLINE DIMENSIONS ORDERING GUIDE