Datasheet AD7767 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 24-Bit, 15 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs |
| Páginas / Página | 25 / 5 — AD7767. Parameter Test. Conditions/Comments. Min. Typ. Max. Unit |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 2.0 Mb |
| Idioma del documento | Inglés |
AD7767. Parameter Test. Conditions/Comments. Min. Typ. Max. Unit
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AD7767 Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL FILTER RESPONSE1 Group Delay 37/ODR μs Settling Time (Latency) Complete settling 74/ODR μs Pass-Band Ripple ±0.005 dB Pass Band 0.453 × ODR Hz −3 dB Bandwidth 0.49 × ODR Hz Stop-Band Frequency 0.547 × ODR Hz Stop-Band Attenuation 100 dB REFERENCE INPUT1 VREF+ Input Voltage 2.4 2 × AVDD V DIGITAL INPUTS (Logic Levels)1 VIL −0.3 +0.3 × VDRIVE V VIH 0.7 × VDRIVE VDRIVE + 0.3 V Input Leakage Current ±1 μA/pin Input Capacitance 5 pF Master Clock Rate 1.024 MHz Serial Clock Rate 1/t8 Hz DIGITAL OUTPUTS1 Data Format Serial 24 bits, twos complement (MSB first) VOL ISINK = +500 μA 0.4 V VOH ISOURCE = −500 μA VDRIVE – 0.3 V POWER REQUIREMENTS1 AVDD ± 5% 2.5 V DVDD ± 5% 2.5 V VDRIVE 1.7 2.5 3.6 V CURRENT SPECIFICATIONS MCLK = 1.024 MHz AD7767 Operational Current 128 kHz output data rate AIDD 1.3 1.5 mA DIDD 3.9 4.8 mA IREF 0.35 0.425 mA AD7767-1 Operational Current 64 kHz output data rate AIDD 1.3 1.5 mA DIDD 2.2 2.85 mA IREF 0.35 0.425 mA AD7767-2 Operational Current 32 kHz output data rate AIDD 1.3 1.5 mA DIDD 1.37 1.86 mA IREF 0.35 0.425 mA Static Current with MCLK Stopped For all devices AIDD 0.9 1 mA DIDD 1 93 μA Power-Down Mode Current For all devices AIDD 0.1 6 μA DIDD 1 93 μA POWER DISSIPATION MCLK = 1.024 MHz AD7767 Operational Power 128 kHz output data rate 15 18 mW AD7767-1 Operational Power 64 kHz output data rate 10.5 13 mW AD7767-2 Operational Power 32 kHz output data rate 8.5 10.5 mW 1 Specifications are for all devices, AD7767, AD7767-1, and AD7767-2. 2 See the Terminology section. Rev. C | Page 4 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION AD7767/AD7767-1/AD7767-2 TRANSFER FUNCTION CONVERTER OPERATION ANALOG INPUT STRUCTURE SUPPLY AND REFERENCE VOLTAGES AD7767 INTERFACE INITIAL POWER-UP READING DATA POWER-DOWN, RESET, AND SYNCHRONIZATION DAISY CHAINING READING DATA IN DAISY-CHAIN MODE CHOOSING THE SCLK FREQUENCY DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS DRIVING THE AD7767 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SIGNAL SOURCE ANTIALIASING POWER DISSIPATION VREF+ INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS OUTLINE DIMENSIONS ORDERING GUIDE
AD7767 Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL FILTER RESPONSE1 Group Delay 37/ODR μs Settling Time (Latency) Complete settling 74/ODR μs Pass-Band Ripple ±0.005 dB Pass Band 0.453 × ODR Hz −3 dB Bandwidth 0.49 × ODR Hz Stop-Band Frequency 0.547 × ODR Hz Stop-Band Attenuation 100 dB REFERENCE INPUT1 VREF+ Input Voltage 2.4 2 × AVDD V DIGITAL INPUTS (Logic Levels)1 VIL −0.3 +0.3 × VDRIVE V VIH 0.7 × VDRIVE VDRIVE + 0.3 V Input Leakage Current ±1 μA/pin Input Capacitance 5 pF Master Clock Rate 1.024 MHz Serial Clock Rate 1/t8 Hz DIGITAL OUTPUTS1 Data Format Serial 24 bits, twos complement (MSB first) VOL ISINK = +500 μA 0.4 V VOH ISOURCE = −500 μA VDRIVE – 0.3 V POWER REQUIREMENTS1 AVDD ± 5% 2.5 V DVDD ± 5% 2.5 V VDRIVE 1.7 2.5 3.6 V CURRENT SPECIFICATIONS MCLK = 1.024 MHz AD7767 Operational Current 128 kHz output data rate AIDD 1.3 1.5 mA DIDD 3.9 4.8 mA IREF 0.35 0.425 mA AD7767-1 Operational Current 64 kHz output data rate AIDD 1.3 1.5 mA DIDD 2.2 2.85 mA IREF 0.35 0.425 mA AD7767-2 Operational Current 32 kHz output data rate AIDD 1.3 1.5 mA DIDD 1.37 1.86 mA IREF 0.35 0.425 mA Static Current with MCLK Stopped For all devices AIDD 0.9 1 mA DIDD 1 93 μA Power-Down Mode Current For all devices AIDD 0.1 6 μA DIDD 1 93 μA POWER DISSIPATION MCLK = 1.024 MHz AD7767 Operational Power 128 kHz output data rate 15 18 mW AD7767-1 Operational Power 64 kHz output data rate 10.5 13 mW AD7767-2 Operational Power 32 kHz output data rate 8.5 10.5 mW 1 Specifications are for all devices, AD7767, AD7767-1, and AD7767-2. 2 See the Terminology section. Rev. C | Page 4 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION RELATED DEVICES TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION AD7767/AD7767-1/AD7767-2 TRANSFER FUNCTION CONVERTER OPERATION ANALOG INPUT STRUCTURE SUPPLY AND REFERENCE VOLTAGES AD7767 INTERFACE INITIAL POWER-UP READING DATA POWER-DOWN, RESET, AND SYNCHRONIZATION DAISY CHAINING READING DATA IN DAISY-CHAIN MODE CHOOSING THE SCLK FREQUENCY DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS DRIVING THE AD7767 DIFFERENTIAL SIGNAL SOURCE SINGLE-ENDED SIGNAL SOURCE ANTIALIASING POWER DISSIPATION VREF+ INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS OUTLINE DIMENSIONS ORDERING GUIDE