Datasheet AD9640 (Analog Devices) - 2

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Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
EVALUATION KITS
• AN-1234: Interfacing the ADL5534 Dual IF Gain Block to • AD9640 Evaluation Board the AD9640 High Speed ADC • AN-282: Fundamentals of Sampled Data Systems • AN-345: Grounding for Low-and-High-Frequency Circuits • AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated • AN-737: How ADIsimADC Models an ADC • AN-741: Little Known Characteristics of Phase Noise • AN-742: Frequency Domain Response of Switched- Capacitor ADCs • AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter • AN-807: Multicarrier WCDMA Feasibility • AN-808: Multicarrier CDMA2000 Feasibility • AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs • AN-835: Understanding High Speed ADC Testing and Evaluation • AN-851: A WiMax Double Downconversion IF Sampling Receiver Design • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual • AN-935: Designing an ADC Transformer-Coupled Front End
Data Sheet
• AD9640: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog- to-Digital Converter Data Sheet
Product Highlight
• Leading Inside Advertorials: Data Converter Function Can Help Solve Cost and Size Design Challenges in 3G and 4G Wireless Infrastructure
TOOLS AND SIMULATIONS
• Visual Analog • AD9640 IBIS Models • AD9627/AD9640 S-Parameters Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150 ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150 DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105 SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150 TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers EXTERNAL MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits[6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits[7:4]—Reserved Bits[3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0] Register 0x107, Bits[7:5]—Reserved Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]Register 0x109, Bits[7:5]—ReservedRegister 0x109, Bits[4:0]—Fine Lower Threshold[12:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits[5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for SM Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits[7:0]—Channel A DC Value[7:0] Register 0x10E, Bits[7:0]—Channel A DC Value[13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits[7:0]—Channel B DC Value[7:0] Register 0x110 Bits[7:0]—Channel B DC Value[13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Power Output Enable Bit 4—Threshold Crossing Output Enable Bits[3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits[6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits[2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0] Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x11B, Bits[7:4]—Reserved Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE