Datasheet AD9601 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter |
| Páginas / Página | 33 / 7 — AD9601. SWITCHING SPECIFICATIONS. Table 4. AD9601-200. AD9601-250. … |
| Formato / tamaño de archivo | PDF / 989 Kb |
| Idioma del documento | Inglés |
AD9601. SWITCHING SPECIFICATIONS. Table 4. AD9601-200. AD9601-250. Parameter (Conditions). Temp. Min. Typ. Max. Unit
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AD9601 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4. AD9601-200 AD9601-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 200 250 MSPS Minimum Conversion Rate Full 40 40 MSPS CLK+ Pulse Width High (tCH) Full 2.15 2.4 1.8 2.0 ns CLK+ Pulse Width Low (tCL) Full 2.15 2.4 1.8 2.0 ns Output, Single Data Port Mode1 Data Propagation Delay (tPD) 25°C 3.7 3.7 ns DCO Propagation Delay (tCPD) 25°C 3.4 3.4 ns Data to DCO Skew (tSKEW) Full 0 0.3 0.55 0 0.3 0.55 ns Latency Full 6 6 Cycles Output, Interleaved Mode2 Data Propagation Delay (tPDA, tPDB) 25°C 3.5 3.5 ns DCO Propagation Delay (tCPDA, tCPDB) 25°C 3.0 3.0 ns Data to DCO Skew (tSKEWA, tSKEWB ) Full 0 0.5 1.1 0 0.5 1.1 ns Latency Full 6 6 Cycles Standby Recovery 25°C 250 250 ns Power-Down Recovery 50 50 μs Aperture Delay (tA) 25°C 0.1 0.1 ns Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms 1 See Figure 2. 2 See Figure 3. Rev. 0 | Page 6 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD9601 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4. AD9601-200 AD9601-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit
Maximum Conversion Rate Full 200 250 MSPS Minimum Conversion Rate Full 40 40 MSPS CLK+ Pulse Width High (tCH) Full 2.15 2.4 1.8 2.0 ns CLK+ Pulse Width Low (tCL) Full 2.15 2.4 1.8 2.0 ns Output, Single Data Port Mode1 Data Propagation Delay (tPD) 25°C 3.7 3.7 ns DCO Propagation Delay (tCPD) 25°C 3.4 3.4 ns Data to DCO Skew (tSKEW) Full 0 0.3 0.55 0 0.3 0.55 ns Latency Full 6 6 Cycles Output, Interleaved Mode2 Data Propagation Delay (tPDA, tPDB) 25°C 3.5 3.5 ns DCO Propagation Delay (tCPDA, tCPDB) 25°C 3.0 3.0 ns Data to DCO Skew (tSKEWA, tSKEWB ) Full 0 0.5 1.1 0 0.5 1.1 ns Latency Full 6 6 Cycles Standby Recovery 25°C 250 250 ns Power-Down Recovery 50 50 μs Aperture Delay (tA) 25°C 0.1 0.1 ns Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms 1 See Figure 2. 2 See Figure 3. Rev. 0 | Page 6 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9601 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE