Datasheet AD9626 (Analog Devices)

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9626 FEATURES APPLICATIONS SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS Wireless and wired broadband communications ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Cable reverse path SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Communications test equipment Excellent linearity Radar and satellite subsystems DNL = ±0.3 LSB typical Power amplifier linearization INL = ±0.7 LSB typical FUNCTIONAL BLOCK DIAGRAM CMOS outputs RBIAS PWDN AGND AVDD (1.8V) Single data port at up to 250 MHz Interleaved dual port @ ½ sample rate up to 125 MHz REFERENCE AD9626 700 MHz full power analog bandwidth On-chip reference, no external decoupling required CML DRVDD DRGND Integrated input buffer and track-and-hold VIN+ TRACK-AND-HOLD VIN– Low power dissipation ADC 12 OUTPUT 12 272 mW @ 170 MSPS 12-BIT STAGING Dx11 TO Dx0 CORE LVDS 364 mW @ 250 MSPS CLK+ CLOCK OVRA Programmable input voltage range CLK– MANAGEMENT OVRB 1.0 V to 1.5 V, 1.25 V nominal SERIAL PORT 1.8 V analog and digital supply operation DCO+ Selectable output data format (offset binary, twos DCO–
001
complement, Gray code) RESET SCLK SDIO CSB
7099- 0
Clock duty cycle stabilizer
Figure 1.
Integrated data capture clock GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD9626 is a 12-bit monolithic sampling analog-to-digital 1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS converter optimized for high performance, low power, and ease with a 70 MHz input. of use. The product operates at up to a 250 MSPS conversion 2. Low Power—Consumes only 364 mW @ 250 MSPS. rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary func- 3. Ease of Use—CMOS output data and output clock signal tions, including a track-and-hold (T/H) and voltage reference, allow interface to current FPGA technology. The on-chip are included on the chip to provide a complete signal reference and sample-and-hold provide flexibility in conversion solution. system design. Use of a single 1.8 V supply simplifies system power supply design. The ADC requires a 1.8 V analog voltage supply and a differen- tial clock for full performance operation. The digital outputs are 4. Serial Port Control—Standard serial port interface supports CMOS compatible and support either twos complement, offset various product functions, such as data formatting, clock binary format, or Gray code. A data clock output is available for duty cycle stabilizer, power-down, gain adjust, and output proper output data timing. test pattern generation. Fabricated on an advanced CMOS process, the AD9626 is 5. Pin-Compatible Family—10-bit pin-compatible family available in a 56-lead LFCSP, specified over the industrial offered as the AD9601. temperature range (−40°C to +85°C).
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Out-of-Range TIMING—SINGLE PORT MODE TIMING—INTERLEAVED MODE fS/2 Spurious LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS AD9626 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE