Datasheet AD7264 (Analog Devices)

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Data Sheet AD7264 FEATURES FUNCTIONAL BLOCK DIAGRAM AV V Dual, simultaneous sampling, 14-bit, 2-channel ADC CC REFA True differential analog inputs AD7264 Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, REF BUF ×24, ×32, ×48, ×64, ×96, ×128 14-BIT VA+ SUCCESSIVE OUTPUT Throughput rate per ADC PGA T/H D APPROXIMATION OUTA V DRIVERS A– ADC 1 MSPS for AD7264 500 kSPS for AD7264-5 SCLK CAL Analog input impedance: >1 GΩ CS REFSEL Wide input bandwidth CONTROL LOGIC G0 G1 −3 dB bandwidth: 1.7 MHz at gain = 2 G2 4 on-chip comparators G3 V SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32 DRIVE 14-BIT Device offset calibration VB+ PGA T/H SUCCESSIVE OUTPUT DOUTB V APPROXIMATION DRIVERS System gain calibration B– ADC PD0/DIN On-chip reference: 2.5 V PD1 BUF PD2 −40°C to +105°C operation VREFB High speed serial interface CA_CBVCC Compatible with SPI, QSPI™, MICROWIRE™, and DSP CA+ OUTPUT COUTA 48-lead LFCSP and LQFP packages C DRIVERS A– COMP CB+ OUTPUT COUTB C DRIVERS B– COMP CA_CB_GND GENERAL DESCRIPTION CC_CDVCC CC+ OUTPUT
The AD7264 is a dual, 14-bit, high speed, low power, successive
C C OUTC DRIVERS C– COMP
approximation ADC that operates from a single 5 V power supply
CD+ OUTPUT COUTD C DRIVERS
and features throughput rates of up to 1 MSPS per on-chip ADC
D– COMP CC_CD_GND
(500 kSPS for the AD7264-5). Two complete ADC functions 01 0 2- allow simultaneous sampling and conversion of two channels.
AGND DGND
673 0 Each ADC is preceded by a true differential analog input with a Figure 1. PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.
PRODUCT HIGHLIGHTS
The AD7264 contains four comparators. Comparator A and Comparator B are optimized for low power, whereas Comparator C 1. Integrated PGA with a variety of flexible gain settings to and Comparator D have fast propagation delays. The AD7264 allow detection and conversion of low level analog signals. features a calibration function to remove any device offset error 2. Each PGA is followed by a dual simultaneous sampling and programmable gain adjust registers to allow input path (for ADC, featuring throughput rates of 1 MSPS per ADC example, sensor) offset and gain compensation. The AD7264 has (500 kSPS for the AD7264-5). The conversion result of an on-chip 2.5 V reference that can be disabled if an external both ADCs is simultaneously available on separate data reference is preferred. The AD7264 is available in 48-lead LFCSP lines or in succession on one data line if only one serial and LQFP packages. port is available. 3. Four integrated comparators that can be used to count The AD7264 is ideally suited for monitoring small amplitude signals from pole sensors in motor control applications. signals from a variety of sensors. The devices include all the 4. Internal 2.5 V reference. functionality needed for monitoring the position feedback signals from a variety of analog encoders used in motor control systems.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION APPLICATIONS INFORMATION GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE