Datasheet AD9230-11 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter |
| Páginas / Página | 29 / 4 — AD9230-11. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter1. Temp. … |
| Formato / tamaño de archivo | PDF / 665 Kb |
| Idioma del documento | Inglés |
AD9230-11. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter1. Temp. Min. Typ. Max. Unit
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AD9230-11 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1. Parameter1 Temp Min Typ Max Unit
RESOLUTION 11 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error 25°C 4.2 mV Full −12 +12 mV Gain Error 25°C 0.89 % FS Full −2.2 +4.3 % FS Differential Nonlinearity (DNL) 25°C ±0.15 LSB Full −0.4 +0.4 LSB Integral Nonlinearity (INL) 25°C ±0.5 LSB Full −0.5 +0.5 LSB TEMPERATURE DRIFT Offset Error Full ±9 μV/°C Gain Error Full 0.019 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 4.3 kΩ Input Capacitance 25°C 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 152 164 mA I 3 DRVDD /SDR Mode4 Full 55 58 mA I 3 DRVDD /DDR Mode5 Full 36 mA Power Dissipation3 Full SDR Mode4 Full 373 400 mW DDR Mode5 Full 338 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9230-11. 5 Double data rate mode; user-programmable feature. See M the emory Map section. Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE
AD9230-11 SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1. Parameter1 Temp Min Typ Max Unit
RESOLUTION 11 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error 25°C 4.2 mV Full −12 +12 mV Gain Error 25°C 0.89 % FS Full −2.2 +4.3 % FS Differential Nonlinearity (DNL) 25°C ±0.15 LSB Full −0.4 +0.4 LSB Integral Nonlinearity (INL) 25°C ±0.5 LSB Full −0.5 +0.5 LSB TEMPERATURE DRIFT Offset Error Full ±9 μV/°C Gain Error Full 0.019 %/°C ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range2 Full 0.98 1.25 1.5 V p-p Input Common-Mode Voltage Full 1.4 V Input Resistance (Differential) Full 4.3 kΩ Input Capacitance 25°C 2 pF POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Currents I 3 AVDD Full 152 164 mA I 3 DRVDD /SDR Mode4 Full 55 58 mA I 3 DRVDD /DDR Mode5 Full 36 mA Power Dissipation3 Full SDR Mode4 Full 373 400 mW DDR Mode5 Full 338 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9230-11. 5 Double data rate mode; user-programmable feature. See M the emory Map section. Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING RBIAS CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS TRANSFER REGISTER MAP OUTLINE DIMENSIONS ORDERING GUIDE