Datasheet AD7262 (Analog Devices) - 10

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Data Sheet AD7262 Pin No. Mnemonic Description
23 PD0/DIN Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts as the data input pin, and all programming is via the control register (see Table 8). Data to be written to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register on the falling edge of SCLK. 35 CS Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5. 48, 47, 46, 45 CA+, CA−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A CB+, CB− and Comparator B. These two comparators have very low power consumption. 13, 14, 15, 16 CC+, CC−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C CD+, CD− and Comparator D. This pair of comparators offers very fast propagation delays. 5, 6, 8, 19, 42 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. Refer all analog input signals and any external reference signal to this AGND voltage. All AGND pins should connect to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and CC_CD_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. CA_CB_GND and CC_CD_GND can be tied to AGND. 28 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5. Connect the DGND pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 30, 29, 26, 25 COUTA, COUTB, Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective COUTC, COUTD comparator. These are digital output pins with logic levels determined by the VDRIVE supply. 32, 31 DOUTA, DOUTB Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During the conversion process, the data output pins are in three-state and, when the conversion is completed, the 19th SCLK edge clocks out the MSB. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for an additional 14 SCLK cycles on either DOUTA or DOUTB following the initial 31 SCLKs, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. 40, 39, 38, 37 G0, G1, G2, G3 Logic Inputs. These pins program the gain setting of the front-end amplifiers. If all four pins are tied low, the PD0 pin acts as a data input pin, DIN, and all programming is made via the control register (see Table 6). 27 VDRIVE Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what voltage the interface operates, including the comparator outputs. Decouple this pin to DGND. 44, 17 CA_CB_GND, Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/ CC_CD_GND AD7262-5. Both the CA_CB_GND pin and the CC_CD_GND pin must connect to the GND plane of a system and can be tied to AGND. The DGND, AGND, CA_CB_GND, and CC_CD_GND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 24 REFSEL Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on- chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7262/AD7262-5 through the VREFA and/or VREFB pin. EPAD Exposed Metal Paddle. The exposed metal paddle on the bottom of the LFCSP package must be soldered to PCB ground for proper heat dissipation and also for noise and mechanical strength benefits. Rev. B | Page 9 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE