Datasheet AD7262 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators |
| Páginas / Página | 33 / 2 — AD7262* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 896 Kb |
| Idioma del documento | Inglés |
AD7262* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. COMPARABLE PARTS. DESIGN RESOURCES. EVALUATION KITS
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AD7262* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES
View a parametric search of comparable parts. • AD7262 Material Declaration • PCN-PDN Information
EVALUATION KITS
• Quality And Reliability • AD7262 Evaluation Board • Symbols and Footprints
DOCUMENTATION DISCUSSIONS Data Sheet
View all AD7262 EngineerZone Discussions. • AD7262: 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
SOFTWARE AND SYSTEMS REQUIREMENTS
• CED1Z FPGA Project for AD7262 with Nios driver
TECHNICAL SUPPORT
Submit a technical question or find your regional support
REFERENCE MATERIALS
number.
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
View a parametric search of comparable parts. • AD7262 Material Declaration • PCN-PDN Information
EVALUATION KITS
• Quality And Reliability • AD7262 Evaluation Board • Symbols and Footprints
DOCUMENTATION DISCUSSIONS Data Sheet
View all AD7262 EngineerZone Discussions. • AD7262: 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
SOFTWARE AND SYSTEMS REQUIREMENTS
• CED1Z FPGA Project for AD7262 with Nios driver
TECHNICAL SUPPORT
Submit a technical question or find your regional support
REFERENCE MATERIALS
number.
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE