Datasheet AD9239 (Analog Devices) - 9

AD9239 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL RESISTANCE Parameter Rating
The exposed paddle must be soldered to the ground plane for Electrical the LFCSP package. Soldering the exposed paddle to the customer AVDD to AGND −0.3 V to +2.0 V board increases the reliability of the solder joints, maximizing DRVDD to DRGND −0.3 V to +2.0 V the thermal capability of the package. AGND to DRGND −0.3 V to +0.3 V
Table 7. Thermal Resistance
AVDD to DRVDD −2.0 V to +2.0 V
Package Type θ
DOUT ± x to DRGND −0.3 V to DRVDD + 0.3 V
JA θJB θJC Unit
72-Lead LFCSP (CP-72-3) 16.2 7.9 0.6 °C/W SDO, SDI/SDIO, CLK± , VIN ± x, −0.3 V to AVDD + 0.3 V VCMx, TEMPOUT, RBIAS to AGND SCLK, CSB, PGMx, RESET, −0.3 V to AVDD + 0.3 V Typical θJA, θJB, and θJC values are specified for a 4-layer board in PDWN to AGND still air. Airflow increases heat dissipation, effectively reducing Environmental θJA. In addition, metal in direct contact with the package leads Storage Temperature Range −65°C to +125°C from metal traces and through holes, ground, and power planes Operating Temperature Range −40°C to +85°C reduces the θJA. Lead Temperature 300°C (Soldering 10 sec)
ESD CAUTION
Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E | Page 8 of 40 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation Digital Start-Up Sequence Minimize Skew and Time Misalignment (Optional) Link Initialization (Required) Digital Outputs and Timing Digital Output Scrambler and Error Code Correction Error Correction Code Scramblers Inverter Balance Example Calculating the Parity Bits for the Hamming Code TEMPOUT Pin RBIAS Pin VCMx Pins RESET Pin PDWN Pin SDO Pin SDI/SDIO Pin SCLK Pin CSB Pin PGMx Pins Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Outline Dimensions Ordering Guide