Datasheet AD7780 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 24-Bit Pin-Programmable Low Power Σ−Δ ADC |
| Páginas / Página | 17 / 6 — AD7780. TIMING CHARACTERISTICS. Table 3. Parameter1. Limit at TMIN, TMAX. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 359 Kb |
| Idioma del documento | Inglés |
AD7780. TIMING CHARACTERISTICS. Table 3. Parameter1. Limit at TMIN, TMAX. Unit. Test Conditions/Comments
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AD7780 TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 3. Parameter1 Limit at TMIN, TMAX Unit Test Conditions/Comments
Read2 t1 100 ns min SCLK high pulse width t2 100 ns min SCLK low pulse width t 3 3 0 ns min SCLK active edge to data valid delay4 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t4 10 ns min SCLK inactive edge to DOUT/RDY high 130 ns max Reset t5 100 ns min PDRST low pulse width t 5 6 FILTER/GAIN change to data valid delay 120 ms typ Update rate = 16.7 Hz 300 ms typ Update rate = 10 Hz 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 The PDRST high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle.
Circuit and Timing Diagrams ISINK (1.6mA WITH DVDD = 5V, PDRST 100µA WITH DVDD = 3V) (INPUT) t5 TO OUTPUT 1.6V PIN
04
50pF DOUT/RDY
0
(OUTPUT)
5- 94 2 07
ISOURCE (200µA WITH DVDD = 5V,
-00
100µA WITH DV
45
DD = 3V)
079 Figure 2. Load Circuit for Timing Characterization Figure 4. Resetting the AD7780
GAIN OR FILTER DOUT/RDY MSB LSB (INPUT) (OUTPUT) t t6 3 t4 t1 DOUT/RDY (OUTPUT)
-005
SCLK
07945
(INPUT)
3 0 0
t
5-
2
94 07 Figure 3. Read Cycle Timing Diagram Figure 5. Changing Gain or Filter Option Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION THEORY OF OPERATION FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET () ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE BRIDGE POWER-DOWN SWITCH DIGITAL INTERFACE APPLICATIONS INFORMATION WEIGH SCALES PERFORMANCE IN A WEIGH SCALE SYSTEM EMI RECOMMENDATIONS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
AD7780 TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 3. Parameter1 Limit at TMIN, TMAX Unit Test Conditions/Comments
Read2 t1 100 ns min SCLK high pulse width t2 100 ns min SCLK low pulse width t 3 3 0 ns min SCLK active edge to data valid delay4 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t4 10 ns min SCLK inactive edge to DOUT/RDY high 130 ns max Reset t5 100 ns min PDRST low pulse width t 5 6 FILTER/GAIN change to data valid delay 120 ms typ Update rate = 16.7 Hz 300 ms typ Update rate = 10 Hz 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 The PDRST high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle.
Circuit and Timing Diagrams ISINK (1.6mA WITH DVDD = 5V, PDRST 100µA WITH DVDD = 3V) (INPUT) t5 TO OUTPUT 1.6V PIN
04
50pF DOUT/RDY
0
(OUTPUT)
5- 94 2 07
ISOURCE (200µA WITH DVDD = 5V,
-00
100µA WITH DV
45
DD = 3V)
079 Figure 2. Load Circuit for Timing Characterization Figure 4. Resetting the AD7780
GAIN OR FILTER DOUT/RDY MSB LSB (INPUT) (OUTPUT) t t6 3 t4 t1 DOUT/RDY (OUTPUT)
-005
SCLK
07945
(INPUT)
3 0 0
t
5-
2
94 07 Figure 3. Read Cycle Timing Diagram Figure 5. Changing Gain or Filter Option Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION THEORY OF OPERATION FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET () ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE BRIDGE POWER-DOWN SWITCH DIGITAL INTERFACE APPLICATIONS INFORMATION WEIGH SCALES PERFORMANCE IN A WEIGH SCALE SYSTEM EMI RECOMMENDATIONS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE