Datasheet AD9267 (Analog Devices) - 9

AD9267 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T + D B B D T F D A A D E K ND ND D – + – + ND N N D IL E D N N D S B CL CG AG AV VI VI AV CF VR AV VI VI AV AG RE CS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CLK– 1 PIN 1 48 SCLK/PLLMULT0 INDICATOR CVDD 2 47 SDIO/PLLMULT1 PDWNA 3 46 PLLMULT2 PDWNB 4 45 PLLMULT3 PLL_LOCKED 5 44 PLLMULT4 AD9267 DVDD 6 43 DVDD DGND 7 42 DGND DRVDD 8 41 DRVDD TOP VIEW D0–B 9 40 D3+A (Not to Scale) D0+B 10 39 D3–A D1–B 11 38 D2+A D1+B 12 37 D2–A D2–B 13 36 D1+A D2+B 14 35 D1–A D3–B 15 34 D0+A D3+B 16 33 D0–A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B B – + D A A – + ND DD – + DNC DNC VD DNC DNC DNC DNC DNC OR OR DCO DCO DG DV OR OR DR NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB
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INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
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THE THERMAL CAPACITY OF THE PACKAGE.
73 77 0 Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1 CLK− Differential Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3, 4 PDWNA, PDWNB Power-Down Pins. Active high. 5 PLL_LOCKED PLL Lock Indicator. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply 9 to 16 D0−B, D0+B to D3−B, D3+B Channel B Differential LVDS Data Output Bits. D0+B is the LSB and D3+B is the MSB. 17, 18 OR−B, OR+B Channel B Overrange Indicator Pins. 19, 20 DCO−, DCO+ Differential Data Clock Output. 21, 22, 26 to 30 DNC Do Not Connect. 31, 32 OR−A, OR+A Channel A Overrange Indicator Pins. 33 to 40 D0−A, D0+A to D3−A, D3+A Channel A Differential LVDS Data Output Bits. D0+A is the LSB and D3+A is the MSB. 44, 45, 46 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins. 47 SDIO/PLLMULT1 Serial Port Interface Data Input/Output/PLL Mode Selection Pins. 48 SCLK/PLLMULT0 Serial Port Interface Clock/PLL Mode Selection Pins. 49 CSB Serial Port Interface Chip Select Pin Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53, 54 VIN+A, VIN−A Channel A Analog Input. 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59, 60 VIN+B, VIN−B Channel B Analog Input. 63 CGND Clock Ground. 64 CLK+ Differential Clock Input (+). 65 Exposed paddle (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed paddle must be soldered to analog ground of the PCB to achieve optimal electrical and thermal performance. Rev. 0 | Page 8 of 24 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Power Dissipation and Standby Mode Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide