Datasheet AD7170 (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | 12-Bit Low Power Σ−Δ ADC |
| Páginas / Página | 15 / 4 — Data Sheet. AD7170. SPECIFICATIONS. Table 1. AD7170B. Parameter. Min. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 373 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD7170. SPECIFICATIONS. Table 1. AD7170B. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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Data Sheet AD7170 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VREF = VDD, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 1. AD7170B 1 Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL Output Data Rate (fADC) 125 Hz Settling time = 3/fADC No Missing Codes2 12 Bits Noise Free Resolution 12 Bits VINx = 0 V, VREF = VDD Resolution Peak-to-Peak (p-p) 12 Bits VINx = 0 V, VREF = VDD Effective Resolution (ENOB) 12 Bits VINx = 0 V, VREF = VDD RMS Noise See Table 6 μV VINx = 0 V, VREF = VDD Integral Nonlinearity ±0.1 LSB Offset Error ±200 µV Offset Error Drift vs. Temperature ±250 nV/°C Full-Scale Error ±0.015 % of FS Gain Drift vs. Temperature ±0.07 LSB/°C Power Supply Rejection 85 dB VINx = 1 V ANALOG INPUTS Differential Input Voltage Range ±VREF V VREF = REFIN(+) − REFIN(−) Absolute AINx Voltage Limits2 GND − 0.03 VDD + 0.03 V Average Input Current2 ±400 nA/V Input current varies with input voltage Average Input Current Drift ±60 pA/V/°C DC Common-Mode Rejection 90 dB VINx = 1 V REFERENCE External REFIN Voltage VDD V REFIN = REFIN(+) − REFIN(−) Reference Voltage Range2 0.5 VDD V Absolute REFIN Voltage Limits2 GND − 0.03 VDD + 0.03 V Average Reference Input Current 400 nA/V Average Reference Input Current ±0.15 nA/V/°C Drift DC Common-Mode Rejection 110 dB INTERNAL CLOCK Frequency2 64 − 5% 64 + 5% kHz LOGIC INPUTS SCLK, PDRST2 Input Low Voltage, VINL 0.4 V VDD = 3 V 0.8 V VDD = 5 V Input High Voltage, VINH 1.8 V VDD = 3 V 2.4 V VDD = 5 V SCLK (Schmitt-Triggered Input)2 Hysteresis 100 mV VDD = 3 V 140 mV VDD = 5 V Input Currents ±2 µA VIN = VDD or GND Input Capacitance 5 pF All digital inputs Rev. B | Page 3 of 14 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET (PDRST\) ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE SYSTEM SIGNAL CONDITIONING CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7170 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VREF = VDD, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 1. AD7170B 1 Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL Output Data Rate (fADC) 125 Hz Settling time = 3/fADC No Missing Codes2 12 Bits Noise Free Resolution 12 Bits VINx = 0 V, VREF = VDD Resolution Peak-to-Peak (p-p) 12 Bits VINx = 0 V, VREF = VDD Effective Resolution (ENOB) 12 Bits VINx = 0 V, VREF = VDD RMS Noise See Table 6 μV VINx = 0 V, VREF = VDD Integral Nonlinearity ±0.1 LSB Offset Error ±200 µV Offset Error Drift vs. Temperature ±250 nV/°C Full-Scale Error ±0.015 % of FS Gain Drift vs. Temperature ±0.07 LSB/°C Power Supply Rejection 85 dB VINx = 1 V ANALOG INPUTS Differential Input Voltage Range ±VREF V VREF = REFIN(+) − REFIN(−) Absolute AINx Voltage Limits2 GND − 0.03 VDD + 0.03 V Average Input Current2 ±400 nA/V Input current varies with input voltage Average Input Current Drift ±60 pA/V/°C DC Common-Mode Rejection 90 dB VINx = 1 V REFERENCE External REFIN Voltage VDD V REFIN = REFIN(+) − REFIN(−) Reference Voltage Range2 0.5 VDD V Absolute REFIN Voltage Limits2 GND − 0.03 VDD + 0.03 V Average Reference Input Current 400 nA/V Average Reference Input Current ±0.15 nA/V/°C Drift DC Common-Mode Rejection 110 dB INTERNAL CLOCK Frequency2 64 − 5% 64 + 5% kHz LOGIC INPUTS SCLK, PDRST2 Input Low Voltage, VINL 0.4 V VDD = 3 V 0.8 V VDD = 5 V Input High Voltage, VINH 1.8 V VDD = 3 V 2.4 V VDD = 5 V SCLK (Schmitt-Triggered Input)2 Hysteresis 100 mV VDD = 3 V 140 mV VDD = 5 V Input Currents ±2 µA VIN = VDD or GND Input Capacitance 5 pF All digital inputs Rev. B | Page 3 of 14 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET (PDRST\) ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE SYSTEM SIGNAL CONDITIONING CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE