Datasheet AD7171 (Analog Devices) - 8

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Data Sheet AD7171 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 GND DOUT/RDY 2 9 PDRST AD7171 AIN(+) 3 8 V TOP VIEW DD (Not to Scale) AIN(–) 4 7 GND REFIN(+) 5 6 REFIN(–)
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NOTES 1. CONNECT EXPOSED PAD TO GROUND.
08417- Figure 5. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data. 2 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to access the data register of the ADC. Eight status bits accompany each data read. See Figure 13 for further details. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If the data is not read after the conversion, the pin goes high before the next update occurs. 3 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−). 4 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−). 5 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(–). The nominal reference voltage (REFIN(+) − REFIN(−)) is 5 V, but the device can function with a reference of 0.5 V to VDD. 6 REFIN(−) Negative Reference Input. 7, 10 GND Ground Reference Point. 8 VDD Supply Voltage, 2.7 V to 5.25 V. 9 PDRST Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is reset and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms approximately to power up. EPAD Exposed Pad. Connect exposed pad to ground. Rev. C | Page 7 of 16 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET (PDRST\) ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE SYSTEM SIGNAL CONDITIONING CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE