Datasheet AD7194 (Analog Devices)

8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA Data Sheet AD7194 FEATURES Pressure measurement Fast settling filter option Temperature measurement 8 differential/16 pseudo differential input channels Flow measurement RMS noise: 11 nV at 4.7 Hz (gain = 128) Weigh scales 15.5 noise-free bits at 2.4 kHz (gain = 128) Chromatography Up to 22 noise-free bits (gain = 1) Medical and scientific instrumentation Offset drift: ±5 nV/°C GENERAL DESCRIPTION Gain drift: ±1 ppm/°C
The AD7194 is a low noise, complete analog front end for high
Programmable gain (1 to 128)
precision measurement applications. It contains a low noise,
Output data rate: 4.7 Hz to 4.8 kHz
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
Internal or external clock Simultaneous 50 Hz/60 Hz rejection
The on-chip low noise gain stage means that signals of small
4 general-purpose digital outputs
amplitude can interface directly to the ADC.
Power supply
The device can be configured to have eight differential inputs or
AVDD: 3 V to 5.25 V
sixteen pseudo differential inputs. The on-chip 4.92 MHz clock
DVDD: 2.7 V to 5.25 V
can be used as the clock source to the ADC or, alternatively, an
Current: 4.65 mA
external clock or crystal can be used. The output data rate from
Temperature range: −40°C to +105°C
the part can be varied from 4.7 Hz to 4.8 kHz.
Package: 32-lead LFCSP
The device has a very flexible digital filter, including a fast
Interface
settling option. Variables such as output data rate and settling
3-wire serial
time are dependent on the option selected. For applications that
SPI, QSPI™, MICROWIRE™, and DSP compatible
require al conversions to be settled, the AD7194 includes zero
Schmitt trigger on SCLK
latency.
APPLICATIONS
The part operates with a power supply from 3 V to 5.25 V. It
PLC/DCS analog input modules
consumes a current of 4.65 mA, and it is housed in a 32-lead
Data acquisition
LFCSP package.
Strain gage transducers FUNCTIONAL BLOCK DIAGRAM AV DV DD AGND DD DGND REFIN1(+) REFIN1(–) REFERENCE AD7194 DETECT AIN1/P3 AVDD AIN2/P2 AIN3/P1/REFIN2(+) AIN4/P0/REFIN2(–) SERIAL DOUT/RDY INTERFACE AIN5 MUX DIN Σ-Δ PGA AND ADC CONTROL SCLK LOGIC AIN16 CS AINCOM AGND CLOCK TEMP CIRCUITRY SENSOR
001
MCLK1 MCLK2
08566- Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED FAST SETTLING ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 Channel Selection (Pseudo Bit = 0) DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX3 GPOCON REGISTER RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter Serial Interface Clock Temperature Sensor Digital Outputs Calibration ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION ENABLE PARITY CLOCK TEMPERATURE SENSOR LOGIC OUTPUTS CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) FAST SETTLING MODE (SINC4 FILTER) Output Data Rate and Settling Time, Sinc4 Filter 50 Hz/60 Hz Rejection, Sinc4 Filter FAST SETTLING MODE (SINC3 FILTER) Output Data Rate and Settling Time, Sinc3 Filter 50 Hz/60 Hz Rejection, Sinc3 Filter FAST SETTLING MODE (CHOP ENABLED) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION FLOWMETER OUTLINE DIMENSIONS ORDERING GUIDE