Datasheet AD7626 (Analog Devices) - 8

Data Sheet AD7626 TIMING DIAGRAMS SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ ACQUISITION ACQUISITION ACQUISITION tCLKL tCLK 15 16 1 2 15 16 1 2 3 CLK– CLK+ tDCO 15 16 1 2 15 16 1 2 3 DCO– DCO+ tMSB t t D CLKD D+
3
D1 D0 D15 D14 D1 D0 D15 D14 0 D13
-00
N – 1 N – 1 0 N N N N N + 1 N + 1 N + 1
48
D–
76 0 Figure 2. Echoed Clock Interface Mode Timing Diagram
SAMPLE N SAMPLE N + 1 tCYC tCNVH CNV– CNV+ ACQUISITION ACQUISITION ACQUISITION t t CLK CLKL 17 18 1 2 3 4 17 18 1 2 3 CLK– CLK+ tMSB tCLKD D+ D1 D0 D15 D14 D1 D0 D15 0 1 0 0 1 0
-004
N – 1 N – 1 N N N N N + 1
48
D–
076 Figure 3. Self Clocked Interface Mode Timing Diagram Rev. D | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER INFORMATION TRANSFER FUNCTIONS ANALOG INPUTS TYPICAL CONNECTION DIAGRAM DRIVING THE AD7626 Differential Analog Input Source Single-Ended to Differential Driver Single-Ended or Fully Differential High Frequency Driver VOLTAGE REFERENCE OPTIONS Wake-Up Time from EN1 = 0, EN0 = 0 POWER SUPPLY Power-Up DIGITAL INTERFACE Conversion Control Echoed Clock Interface Mode Self Clocked Mode APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING Exposed Paddle VDD1 Supply Routing and Decoupling VIO Supply Decoupling Layout and Decoupling of Pin 25 to Pin 32 OUTLINE DIMENSIONS ORDERING GUIDE