Datasheet AD9609 (Analog Devices)

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9609 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIO SCLK CSB DRVDD 1.8 V to 3.3 V output supply SNR RBIAS SPI 61.5 dBFS at 9.7 MHz input VCM R OR 61.0 dBFS at 200 MHz input PROGRAMMING DATA FFE D9 (MSB) SFDR U VIN+ S ADC O CORE T B 75 dBc at 9.7 MHz input VIN– CM U D0 (LSB) TP 73 dBc at 200 MHz input OU DCO Low power VREF 45 mW at 20 MSPS SENSE 76 mW at 80 MSPS REF AD9609 SELECT Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit DIVIDE MODE BY DCS CONTROLS 1 TO 8 2 V p-p differential analog input DNL = ±0.10 LSB
001
Serial port control options CLK+ CLK– PDWN DFS MODE
08541-
Offset binary, gray code, or twos complement data format
Figure 1.
Optional clock duty cycle stabilizer PRODUCT HIGHLIGHTS Integer 1-to-8 input clock divider
1. The AD9609 operates from a single 1.8 V analog power
Built-in selectable digital test pattern generation
supply and features a separate digital output driver supply
Energy-saving power-down modes
to accommodate 1.8 V to 3.3 V logic families.
Data clock out with programmable clock and data alignment
2. The sample-and-hold circuit maintains excel ent performance for input frequencies up to 200 MHz and is designed for low
APPLICATIONS
cost, low power, and ease of use.
Communications
3. A standard serial port interface supports various product
Diversity radio systems
features and functions, such as data output formatting,
Multimode digital receivers
internal clock divider, power-down, DCO and data output
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
(D9 to D0) timing and offset adjustments, and voltage
Smart antenna systems
reference modes.
Battery-powered instruments
4. The AD9609 is packaged in a 32-lead RoHS compliant
Handheld scope meters
LFCSP that is pin compatible with the AD9629 12-bit ADC
Portable medical imaging
and the AD9649 14-bit ADC, enabling a simple migration
Ultrasound
path between 10-bit and 14-bit converters sampling from
Radar/LIDAR
20 MSPS to 80 MSPS.
PET/SPECT imaging Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9609-80 AD9609-65 AD9609-40 AD9609-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE