Datasheet AD7195 (Analog Devices) - 5

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AD7195 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments1
External Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 67 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 95 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 95 dB 60 Hz output data rate, 60 ± 1 Hz ANALOG INPUTS Differential Input Voltage ±VREF/gain V VREF = REFIN(+) − REFIN(−), gain = 1 to 128 Ranges −(AVDD − +(AVDD − V Gain > 1 1.25 V)/gain 1.25 V)/gain Absolute AIN Voltage Limits2 Unbuffered Mode AGND − 0.05 AVDD + 0.05 V Buffered Mode AGND + 0.25 AVDD − 0.25 V Analog Input Current Buffered Mode Input Current2 −2 +2 nA Gain = 1 −4.5 +4.5 nA Gain > 1 Input Current Drift ±5 pA/°C Unbuffered Mode Input Current ±5 µA/V Gain = 1, input current varies with input voltage ±1 µA/V Gain > 1 Input Current Drift ±0.05 nA/V/°C External clock ±1.6 nA/V/°C Internal clock REFERENCE INPUT REFIN Voltage 1 AVDD AVDD V REFIN = REFIN(+) − REFIN(−). The differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1 Absolute REFIN Voltage GND − 0.05 AVDD + 0.05 V Limits2 Average Reference Input 7 µA/V Current Average Reference Input ±0.03 nA/V/°C External clock Current Drift ±1.3 nA/V/°C Internal clock Normal Mode Rejection2 Same as for analog inputs Common-Mode Rejection 95 dB Reference Detect Levels 0.3 0.6 V TEMPERATURE SENSOR Accuracy ±2 °C Applies after user calibration at 25°C Sensitivity 2815 Codes/°C Bipolar mode BRIDGE POWER-DOWN SWITCH RON 10 Ω Allowable Current2 30 mA Continuous current BURNOUT CURRENTS AIN Current 500 nA Analog inputs must be buffered and chop disabled DIGITAL OUTPUTS (ACXx, ACXx ) Output High Voltage, V 2 OH 4 V AVDD = 5 V, ISOURCE = 200 µA Output Low Voltage, V 2 OL 0.4 V AVDD = 5 V, ISINK = 800 µA INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.72 5.12 MHz Duty Cycle 50:50 % External Clock/Crystal2 Frequency 2.4576 4.9152 5.12 MHz Input Low Voltage VINL 0.8 V DVDD = 5 V 0.4 V DVDD = 3 V Input High Voltage, VINH 2.5 V DVDD = 3 V 3.5 V DVDD = 5 V Input Current −10 +10 µA Rev. A | Page 4 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE