Datasheet AD9261 (Analog Devices) - 9

AD9261 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D T D K+ ND ND D – + ND N N D IL EF D B CL CG AG AV VI VI AV CF VR AV AG CS 48 47 46 45 44 43 42 41 40 39 38 37 CLK– 1 36 PLLMULT0/SCLK PIN 1 CVDD 2 35 PLLMULT1/SDIO INDICATOR PDWN 3 34 PLLMULT2 DVDD 4 33 PLLMULT3 DGND 5 32 PLLMULT4 AD9261 DRVDD 6 31 DVDD PLL_LOCKED 7 TOP VIEW 30 DGND DCO 8 (Not to Scale) 29 DRVDD D0 9 28 OR D1 10 27 D15 D2 11 26 D14 D3 12 25 D13 13 14 15 16 17 18 19 20 21 22 23 24 D D 1 D4 D5 D6 D7 D ND D D8 D9 V D10 D1 D12 DG DV DR NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB
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INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
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THE THERMAL CAPACITY OF THE PACKAGE.
78 0 Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 PDWN External Power-Down Pin. 4, 19, 31 DVDD Digital Supply (1.8 V). 5, 18, 30 DGND Digital Ground. 6, 17, 29 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 7 PLL_LOCKED PLL Lock Indicator. 8 DCO Data Clock Output. 9 to 16, 20 to 27 D0 to D15 Data Output Bits. D0 is the LSB and D15 is the MSB. 28 OR Overrange Indicator. 32, 33, 34 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins. 35 PLLMULT1/SDIO PLL Mode Selection Pin/Serial Port Interface Data Input/Output. 36 PLLMULT0/SCLK PLL Mode Selection Pin/Serial Port Interface Clock. 37 CSB Serial Port Interface Chip Select. Active low. 38, 46 AGND Analog Ground. 39, 42, 45 AVDD Analog Supply (1.8 V). 40 VREF Voltage Reference Input/Output. 41 CFILT Noise Limiting Filter Capacitor. 43 VIN+ Analog Input (+). 44 VIN– Analog Input (−). 47 CGND Clock Ground. 48 CLK+ Clock Input (+). 49 EPAD Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package. Rev. 0 | Page 8 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide