Datasheet AD7606, AD7606-6, AD7606-4 (Analog Devices) - 8

link to page 9 link to page 9
AD7606/AD7606-6/AD7606-4 Data Sheet Limit at TMIN, TMAX Limit at TMIN, TMAX (0.1 × VDRIVE and (0.3 × VDRIVE and 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description
t13 Delay from CS until DB[15:0] three-state disabled 16 19 ns VDRIVE above 4.75 V 20 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 37 ns VDRIVE above 2.3 V t 4 14 Data access time after RD falling edge 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t15 6 6 ns Data hold time after RD falling edge t16 6 6 ns CS to DB[15:0] hold time t17 22 22 ns Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 23.5 20 MHz VDRIVE above 4.75 V 17 15 MHz VDRIVE above 3.3 V 14.5 12.5 MHz VDRIVE above 2.7 V 11.5 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 30 35 ns VDRIVE = 2.3 V to 2.7 V t 4 19 Data access time after SCLK rising edge 17 20 ns VDRIVE above 4.75 V 23 26 ns VDRIVE above 3.3 V 27 32 ns VDRIVE above 2.7 V 34 39 ns VDRIVE above 2.3 V t20 0.4 tSCLK 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK 0.4 tSCLK ns SCLK high pulse width t22 7 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three- state disabled 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 15 18 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 16 19 ns VDRIVE above 4.75 V 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns VDRIVE above 2.3 V Rev. C | Page 8 of 36 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (PAR/SER/BYTE SEL = 0) Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) Serial Interface (PAR/SER/BYTE SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide