Datasheet AD9650 (Analog Devices) - 4

Data Sheet AD9650 SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled, unless otherwise noted.
Table 1. AD9650BCPZ-25 AD9650BCPZ-65 AD9650BCPZ-80 AD9650BCPZ-105 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 16 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Guaranteed Offset Error Full ±0.2 ±0.5 ±0.2 ±0.5 ±0.4 ±0.70 ±0.4 ±0.7 % FSR Gain Error Full ±0.4 ±2.5 ±0.4 ±2.5 ±0.4 ±2.5 ±0.4 ±2.5 % FSR Differential Nonlinearity (DNL)1 Full −1 +1.3 −1 +1.3 −1 +1.3 −1 +1.3 LSB 25°C ±0.7 ±0.7 ±0.7 ±0.7 LSB Integral Nonlinearity (INL)1 Full ±3 ±5 ±6 ±6 LSB 25°C ±1.6 ±2.5 ±2.5 ±3 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±0.4 ±0.1 ±0.4 ±0.1 ±0.4 ±0.1 ±0.4 % FSR Gain Error Full ±0.5 ±1.3 ±0.5 ±1.3 ±0.5 ±1.3 ±0.5 ±1.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ±2 ppm/°C Gain Error Full ±15 ±15 ±15 ±15 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1.35 V Full ±7 ±14 ±7 ±14 ±7 ±14 ±7 ±14 mV Mode) Load Regulation at 1.0 mA Full 10 10 10 10 mV INPUT REFERRED NOISE VREF = 1.35 V 25°C 1.5 1.5 1.5 1.5 LSB rms ANALOG INPUT Input Span, VREF = 1.35 V Full 2.7 2.7 2.7 2.7 V p-p Input Capacitance2 Full 11 11 11 11 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 0.9 V REFERENCE INPUT RESISTANCE Full 6 6 6 6 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD1 Full 125 131 202 209 267 275 332 340 mA IDRVDD1 (1.8 V CMOS) Full 8 23 29 36 mA IDRVDD1 (1.8 V LVDS) Full 72 86 90 100 mA POWER CONSUMPTION DC Input Full 237 254 397 408 522 537 656 675 mW Sine Wave Input1 (DRVDD = Full 240 405 533 663 mW 1.8 V CMOS Output Mode) Sine Wave Input1 (DRVDD = Full 355 520 642 778 mW 1.8 V LVDS Output Mode) Standby Power3 Full 50 50 50 50 mW Power-Down Power Full 0.25 2.5 0.25 2.5 0.25 2.5 0.25 2.5 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND). Rev. B | Page 3 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9650-25 AD9650-65 AD9650-80 AD9650-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Large-Signal FFT Small-Signal FFT Static Linearity Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only Bit 1—Clock Divider SYNC Enable Bit 0—Master SYNC Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE