Datasheet AD7298 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor |
| Páginas / Página | 25 / 6 — AD7298. TIMING SPECIFICATIONS. Table 2. Parameter Limit. TMIN, TMAX. Unit … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 457 Kb |
| Idioma del documento | Inglés |
AD7298. TIMING SPECIFICATIONS. Table 2. Parameter Limit. TMIN, TMAX. Unit Test. Conditions/Comments
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AD7298 TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal; TA = −40°C to + 125°C, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments
tCONVERT t2 + (16 × tSCLK) μs max Conversion time 820 ns typ Each ADC channel VIN0 to VIN7, fSCLK = 20 MHz 100 μs max Temperature sensor channel f 1 SCLK 50 kHz min Frequency of external serial clock 20 MHz max Frequency of external serial clock tQUIET 6 ns min Minimum quiet time required between the end of serial read and the start of the next voltage conversion in repeat and nonrepeat mode. t2 10 ns min CS to SCLK setup time t 1 3 15 ns max Delay from CS (falling edge) until DOUT three-state disabled t 1 4 Data access time after SCLK falling edge 35 ns max VDRIVE = 1.65 V to 3 V 28 ns max VDRIVE = 3 V to 3.6 V t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t 1 7 14 ns min SCLK to DOUT valid hold time t 1 8 16/34 ns min/max SCLK falling edge to DOUT high impedance t9 5 ns min DIN setup time prior to SCLK falling edge t10 4 ns min DIN hold time after SCLK falling edge t11 100 ns min TSENSE_BUSY falling edge to CS falling edge t 1 12 30 ns max Delay from CS rising edge to DOUT high impedance tPOWER-UP_PARTIAL 1 μs max Power-up time from partial power-down tPOWER-UP 6 ms max Internal reference power-up time from full power-down 1 Measured with a load capacitance on DOUT of 15 pF. Rev. B | Page 5 of 24 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION THERMAL RESISTANCE PIN CONFIGURATION AND FUNCTION DESCRIPTION TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT ADC Transfer Function TEMPERATURE SENSOR OPERATION TEMPERATURE SENSOR AVERAGING Temperature Value Format VDRIVE THE INTERNAL OR EXTERNAL REFERENCE CONTROL REGISTER MODES OF OPERATION TRADITIONAL MULTICHANNEL MODE OF OPERATION REPEAT OPERATION POWER-DOWN MODES Normal Mode Partial Power-Down Mode Full Power-Down Mode POWERING UP THE AD7298 RESET SERIAL INTERFACE TEMPERATURE SENSOR READ LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING TEMPERATURE MONITORING OUTLINE DIMENSIONS ORDERING GUIDE
AD7298 TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal; TA = −40°C to + 125°C, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments
tCONVERT t2 + (16 × tSCLK) μs max Conversion time 820 ns typ Each ADC channel VIN0 to VIN7, fSCLK = 20 MHz 100 μs max Temperature sensor channel f 1 SCLK 50 kHz min Frequency of external serial clock 20 MHz max Frequency of external serial clock tQUIET 6 ns min Minimum quiet time required between the end of serial read and the start of the next voltage conversion in repeat and nonrepeat mode. t2 10 ns min CS to SCLK setup time t 1 3 15 ns max Delay from CS (falling edge) until DOUT three-state disabled t 1 4 Data access time after SCLK falling edge 35 ns max VDRIVE = 1.65 V to 3 V 28 ns max VDRIVE = 3 V to 3.6 V t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t 1 7 14 ns min SCLK to DOUT valid hold time t 1 8 16/34 ns min/max SCLK falling edge to DOUT high impedance t9 5 ns min DIN setup time prior to SCLK falling edge t10 4 ns min DIN hold time after SCLK falling edge t11 100 ns min TSENSE_BUSY falling edge to CS falling edge t 1 12 30 ns max Delay from CS rising edge to DOUT high impedance tPOWER-UP_PARTIAL 1 μs max Power-up time from partial power-down tPOWER-UP 6 ms max Internal reference power-up time from full power-down 1 Measured with a load capacitance on DOUT of 15 pF. Rev. B | Page 5 of 24 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION THERMAL RESISTANCE PIN CONFIGURATION AND FUNCTION DESCRIPTION TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT ADC Transfer Function TEMPERATURE SENSOR OPERATION TEMPERATURE SENSOR AVERAGING Temperature Value Format VDRIVE THE INTERNAL OR EXTERNAL REFERENCE CONTROL REGISTER MODES OF OPERATION TRADITIONAL MULTICHANNEL MODE OF OPERATION REPEAT OPERATION POWER-DOWN MODES Normal Mode Partial Power-Down Mode Full Power-Down Mode POWERING UP THE AD7298 RESET SERIAL INTERFACE TEMPERATURE SENSOR READ LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING TEMPERATURE MONITORING OUTLINE DIMENSIONS ORDERING GUIDE