Datasheet AD9434 (Analog Devices) - 10

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Data Sheet AD9434 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS + – ND DD DD K– K+ DD D2+ D2– D1+ D1– D0+ D0– DCO DCO DRG DRV AV CL CL AV 56 55 54 53 52 51 50 49 48 47 46 45 44 43 D3– 1 PIN 1 42 AVDD INDICATOR D3+ 2 41 AVDD D4– 3 40 CML D4+ 4 39 AVDD D5– 5 38 AVDD D5+ 6 37 AVDD AD9434 DRVDD 7 36 VIN– DRGND 8 TOP VIEW 35 VIN+ D6– 9 (Not to Scale) 34 AVDD D6+ 10 33 AVDD D7– 11 32 AVDD D7+ 12 31 VREF D8– 13 PIN 0 (EXPOSED PADDLE) = AGND 30 AVDD D8+ 14 29 PWDN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 O S B R– R+ D9– D9+ ND DD DI D10– D10+ D11– O D11+ O S DF CS DNC K/ DRG DRV CL S NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. AGND AND DRGND SHOULD BE TIED TO A COMMON
004
QUIET GROUND PLANE. 3. THE EXPOSED PADDLE MUST BE SOLDERED TO A GROUND PLANE.
09383- Figure 4. Pin Configuration—Single Data Rate Mode
Table 7. Pin Function Descriptions—Single Data Rate Mode Pin No. Mnemonic Description
0 AGND1 Analog Ground. The exposed paddle must be soldered to a ground plane. 30, 32 to 34, 37 to 39, AVDD 1.8 V Analog Supply. 41 to 43, 46 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 28 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating. 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 29 PWDN Chip Power-Down. 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0− D0 Complement Output (LSB). 52 D0+ D0 True Output (LSB). 53 D1− D1 Complement Output. 54 D1+ D1 True Output. 55 D2− D2 Complement Output. 56 D2+ D2 True Output. 1 D3− D3 Complement Output. 2 D3+ D3 True Output. 3 D4− D4 Complement Output. Rev. B | Page 9 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input and Voltage Reference Differential Input Configurations Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) Timing VREF AD9434 Configuration Using the SPI Using the AD9434 to Replace the AD9230 Hardware Interface Configuration Without the SPI Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide