Datasheet AD9484 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter |
| Páginas / Página | 25 / 8 — AD9484. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 637 Kb |
| Idioma del documento | Inglés |
AD9484. ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating. THERMAL RESISTANCE. Table 6. Package Type. θJA. θJC Unit. ESD CAUTION
Línea de modelo para esta hoja de datos
Versión de texto del documento
AD9484 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− through D7+/D7− −0.3 V to DRVDD + 0.2 V
THERMAL RESISTANCE
to DRGND The exposed paddle must be soldered to the ground plane for DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed paddle to the PCB OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V increases the reliability of the solder joints, maximizing the CLK+ to AGND −0.3 V to AVDD + 0.2 V thermal capability of the package. CLK− to AGND −0.3 V to AVDD + 0.2 V VIN+ to AGND −0.3 V to AVDD + 0.2 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SDIO/DCS to DRGND −0.3 V to DRVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W PDWN to AGND −0.3 V to DRVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In CML to AGND −0.3 V to AVDD + 0.2 V addition, metal in direct contact with the package leads from VREF to AGND −0.3 V to AVDD + 0.2 V metal traces, through holes, ground, and power planes reduces Environmental the θJA. Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. A | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE
Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress Electrical rating only; functional operation of the device at these or any AVDD to AGND −0.3 V to +2.0 V other conditions above those indicated in the operational DRVDD to DRGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute AGND to DRGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AVDD to DRVDD −2.0 V to +2.0 V device reliability. D0+/D0− through D7+/D7− −0.3 V to DRVDD + 0.2 V
THERMAL RESISTANCE
to DRGND The exposed paddle must be soldered to the ground plane for DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed paddle to the PCB OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V increases the reliability of the solder joints, maximizing the CLK+ to AGND −0.3 V to AVDD + 0.2 V thermal capability of the package. CLK− to AGND −0.3 V to AVDD + 0.2 V VIN+ to AGND −0.3 V to AVDD + 0.2 V
Table 6.
VIN− to AGND −0.3 V to AVDD + 0.2 V
Package Type θJA θJC Unit
SDIO/DCS to DRGND −0.3 V to DRVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W PDWN to AGND −0.3 V to DRVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In CML to AGND −0.3 V to AVDD + 0.2 V addition, metal in direct contact with the package leads from VREF to AGND −0.3 V to AVDD + 0.2 V metal traces, through holes, ground, and power planes reduces Environmental the θJA. Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C
ESD CAUTION
Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. A | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE