Datasheet AD7609 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC |
| Páginas / Página | 37 / 10 — Data Sheet. AD7609. Limit at TMIN, TMAX. Parameter. Min. Typ. Max. Unit. … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 893 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD7609. Limit at TMIN, TMAX. Parameter. Min. Typ. Max. Unit. Description. Timing Diagrams. CONVST A/. CONVST B. tCYCLE. tCONV. BUSY
Línea de modelo para esta hoja de datos
Versión de texto del documento
Data Sheet AD7609 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description
t27 Delay from RD falling edge to FRSTDATA low 22 ns VDRIVE = 3.3 V to 5.25 V 29 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 18th SCLK falling edge to FRSTDATA low 20 ns VDRIVE = 3.3 V to 5.25 V 27 ns VDRIVE = 2.3 V to 2.7 V t29 29 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams t5 CONVST A/ CONVST B tCYCLE t2 CONVST A/ CONVST B t3 tCONV t1 BUSY t4 CS t7 tRESET
002
RESET
09760- Figure 2. CONVST x Timing—Reading After a Conversion
t5 CONVST A/ CONVST B tCYCLE t2 CONVST A/ CONVST B t3 tCONV t1 BUSY t6 CS t7 tRESET RESET
003 09760- Figure 3. CONVST x Timing—Reading During a Conversion
CS t9 t8 t t 11 10 RD t16 t13 t t 14 17 t15 DATA: V1 V1 V2 V2 V8 V8 DB[15:0] INVALID [17:2] [1:0] [17:2] [1:0] [17:2] [1:0] t26 t27 t29 t24
004
FRSTDATA
09760- Figure 4. Parallel Mode Separate CS and RD Pulses Rev. B | Page 9 of 36 Document Outline Features Applications Companion Products Functional Block Diagram Table of Contents Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference External Reference Mode Internal Reference Mode Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (/PAR/SER SEL = 0) Serial Interface (/PAR/SER SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide
t27 Delay from RD falling edge to FRSTDATA low 22 ns VDRIVE = 3.3 V to 5.25 V 29 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 18th SCLK falling edge to FRSTDATA low 20 ns VDRIVE = 3.3 V to 5.25 V 27 ns VDRIVE = 2.3 V to 2.7 V t29 29 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams t5 CONVST A/ CONVST B tCYCLE t2 CONVST A/ CONVST B t3 tCONV t1 BUSY t4 CS t7 tRESET
002
RESET
09760- Figure 2. CONVST x Timing—Reading After a Conversion
t5 CONVST A/ CONVST B tCYCLE t2 CONVST A/ CONVST B t3 tCONV t1 BUSY t6 CS t7 tRESET RESET
003 09760- Figure 3. CONVST x Timing—Reading During a Conversion
CS t9 t8 t t 11 10 RD t16 t13 t t 14 17 t15 DATA: V1 V1 V2 V2 V8 V8 DB[15:0] INVALID [17:2] [1:0] [17:2] [1:0] [17:2] [1:0] t26 t27 t29 t24
004
FRSTDATA
09760- Figure 4. Parallel Mode Separate CS and RD Pulses Rev. B | Page 9 of 36 Document Outline Features Applications Companion Products Functional Block Diagram Table of Contents Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference External Reference Mode Internal Reference Mode Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (/PAR/SER SEL = 0) Serial Interface (/PAR/SER SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide