Datasheet AD9642 (Analog Devices) - 10

Data Sheet AD9642 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D D D D D D + – N N D D M AV AV VI VI AV AV VC DNC 32 31 30 29 28 27 26 25 CLK+ 1 24 CSB CLK– 2 23 SCLK AVDD 3 AD9642 22 SDIO D0–/D1– (LSB) 4 INTERLEAVED 21 DCO+ D0+/D1+ (LSB) 5 LVDS 20 DCO– D2–/D3– 6 TOP VIEW 19 D12+/D13+ (MSB) D2+/D3+ 7 (Not to Scale) 18 D12–/D13– (MSB) DRVDD 8 17 DRVDD 9 10 11 12 13 14 15 16 + 1– 1 1 1 /D5– /D5+ /D7– /D7+ /D9– /D9+ D /D D4– D4+ D6– D6+ D8– D8+ 0–/ 1 D D10+ NOTES 1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE
03
PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
0 5-
GROUND FOR PROPER OPERATION.
99
2. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
09 Figure 3. LFCSP Pin Configuration (Top View)
Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description
ADC Power Supplies 8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND, Ground Analog Ground. The exposed thermal paddle on the bottom of the package provides Exposed Paddle the analog ground for the part. This exposed paddle must be connected to ground for proper operation. 25 DNC Do Not Connect. Do not connect to this pin. ADC Analog 30 VIN+ Input Differential Analog Input Pin (+). 29 VIN− Input Differential Analog Input Pin (−). 26 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. Digital Outputs 5 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/1—True. 4 D0−/D1− (LSB) Output DDR LVDS Output Data 0/1—Complement. 7 D2+/D3+ Output DDR LVDS Output Data 2/3—True. 6 D2−/D3− Output DDR LVDS Output Data 2/3—Complement. 10 D4+/D5+ Output DDR LVDS Output Data 4/5—True. 9 D4−/D5− Output DDR LVDS Output Data 4/5—Complement. 12 D6+/D7+ Output DDR LVDS Output Data 6/7—True. 11 D6−/D7− Output DDR LVDS Output Data 6/7—Complement. 14 D8+/D9+ Output DDR LVDS Output Data 8/9—True. 13 D8−/D9− Output DDR LVDS Output Data 8/9—Complement. 16 D10+/D11+ Output DDR LVDS Output Data 10/11—True. 15 D10−/D11− Output DDR LVDS Output Data 10/11—Complement. 19 D12+/D13+ (MSB) Output DDR LVDS Output Data 12/13—True. 18 D12−/D13− (MSB) Output DDR LVDS Output Data 12/13—Complement. 21 DCO+ Output LVDS Data Clock Output—True. 20 DCO− Output LVDS Data Clock Output—Complement. SPI Control 23 SCLK Input SPI Serial Clock. 22 SDIO Input/output SPI Serial Data I/O. 24 CSB Input SPI Chip Select (Active Low). Rev. B | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE