Datasheet AD9253 (Analog Devices)

Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Data Sheet AD9253 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD 1.8 V supply operation Low power: 110 mW per channel at 125 MSPS with scalable 14 SERIAL D0+A VIN+A PIPELINE DIGITAL LVDS D0–A power options VIN–A ADC SERIALIZER SERIAL D1+A SNR = 74 dB (to Nyquist) 14 LVDS D1–A VIN+B SFDR = 90 dBc (to Nyquist) PIPELINE DIGITAL SERIAL D0+B VIN–B ADC SERIALIZER LVDS D0–B DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical) RBIAS SERIAL D1+B Serial LVDS (ANSI-644, default) and low power, reduced VREF LVDS D1–B SENSE signal option (similar to IEEE 1596.3) FCO+ REF 1V AD9253 FCO– 650 MHz full power analog bandwidth SELECT AGND SERIAL D0+C 14 LVDS 2 V p-p input voltage range D0–C VIN+C PIPELINE DIGITAL SERIAL D1+C Serial port control VIN–C ADC SERIALIZER LVDS D1–C Full chip and individual channel power-down modes 14 SERIAL D0+D VIN+D PIPELINE DIGITAL LVDS D0–D Flexible bit orientation VIN–D ADC SERIALIZER SERIAL D1+D Built-in and custom digital test pattern generation LVDS D1–D SERIAL PORT CLOCK DCO+ Multichip sync and clock divider VCM INTERFACE MANAGEMENT DCO– Programmable output clock and data alignment Programmable output resolution B M C + – L TP K K Standby mode CS /O /D SYN CL CL
01 0
IO LK C
0065-
SD APPLICATIONS S
1 Figure 1.
Medical ultrasound High speed imaging Quadrature radio receivers
as programmable output clock and data alignment and digital
Diversity radio receivers
test pattern generation. The available digital test patterns
Test equipment
include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port
GENERAL DESCRIPTION
interface (SPI). The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS The AD9253 is available in a RoHS-compliant, 48-lead LFCSP. analog-to-digital converter (ADC) with an on-chip sample- It is specified over the industrial temperature range of −40°C to and-hold circuit designed for low cost, low power, small size, +85°C. This product is protected by a U.S. patent. and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic
PRODUCT HIGHLIGHTS
performance and low power in applications where a small 1. Small Footprint. Four ADCs are contained in a small, space- package size is critical. saving package. The ADC requires a single 1.8 V power supply and LVPECL-/ 2. Low power of 110 mW/channel at 125 MSPS with scalable CMOS-/LVDS-compatible sample rate clock for full performance power options. operation. No external reference or driver components are 3. Pin compatible to the AD9633 12-bit quad ADC. required for many applications. 4. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data The ADC automatically multiplies the sample rate clock for the rate (DDR) operation. appropriate LVDS serial data rate. A data clock output (DCO) for 5. User Flexibility. The SPI control offers a wide range of capturing data on the output and a frame clock output (FCO) flexible features to meet specific system requirements. for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9253-80 AD9253-105 AD9253-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide