Datasheet AD9653 (Analog Devices) - 10

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Data Sheet AD9653 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.
Table 6. Parameter1, 2 Temp Min Typ Max Unit
CLOCK3 Input Clock Rate Full 20 1000 MHz Conversion Rate4 Full 20 125 MSPS Clock Pulse Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)5 Full tFCO + (tSAMPLE/16) ns DCO to Data Delay (tDATA)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps DCO to FCO Delay (tFRAME)5 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps Lane Delay (tLD) 90 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)6 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. E | Page 9 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE